mirror of
https://github.com/tiagovignatti/intel-gpu-tools.git
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igt/gem_concurrent_blit: Exercise wc mappings
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Chris Wilson
Daniel Vetter
parent
d95736906d
commit
f2a045f851
@ -61,6 +61,12 @@ IGT_TEST_DESCRIPTION("Test of pread/pwrite behavior when writing to active"
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int fd, devid, gen;
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struct intel_batchbuffer *batch;
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static void
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nop_release_bo(drm_intel_bo *bo)
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{
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drm_intel_bo_unreference(bo);
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}
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static void
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prw_set_bo(drm_intel_bo *bo, uint32_t val, int width, int height)
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{
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@ -161,6 +167,27 @@ gttX_create_bo(drm_intel_bufmgr *bufmgr, int width, int height)
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return tile_bo(gtt_create_bo(bufmgr, width, height), width);
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}
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static drm_intel_bo *
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wc_create_bo(drm_intel_bufmgr *bufmgr, int width, int height)
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{
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drm_intel_bo *bo;
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igt_require_mmap_wc(fd);
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bo = unmapped_create_bo(bufmgr, width, height);
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bo->virtual = gem_mmap__wc(fd, bo->handle, 0, bo->size, PROT_READ | PROT_WRITE);
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return bo;
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}
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static void
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wc_release_bo(drm_intel_bo *bo)
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{
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munmap(bo->virtual, bo->size);
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bo->virtual = NULL;
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nop_release_bo(bo);
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}
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static drm_intel_bo *
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gpu_create_bo(drm_intel_bufmgr *bufmgr, int width, int height)
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{
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@ -274,26 +301,62 @@ gpu_cmp_bo(drm_intel_bo *bo, uint32_t val, int width, int height, drm_intel_bo *
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cpu_cmp_bo(tmp, val, width, height, NULL);
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}
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struct access_mode {
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const struct access_mode {
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const char *name;
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void (*set_bo)(drm_intel_bo *bo, uint32_t val, int w, int h);
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void (*cmp_bo)(drm_intel_bo *bo, uint32_t val, int w, int h, drm_intel_bo *tmp);
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drm_intel_bo *(*create_bo)(drm_intel_bufmgr *bufmgr, int width, int height);
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const char *name;
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};
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struct access_mode access_modes[] = {
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{ .set_bo = prw_set_bo, .cmp_bo = prw_cmp_bo,
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.create_bo = unmapped_create_bo, .name = "prw" },
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{ .set_bo = cpu_set_bo, .cmp_bo = cpu_cmp_bo,
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.create_bo = unmapped_create_bo, .name = "cpu" },
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{ .set_bo = gtt_set_bo, .cmp_bo = gtt_cmp_bo,
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.create_bo = gtt_create_bo, .name = "gtt" },
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{ .set_bo = gtt_set_bo, .cmp_bo = gtt_cmp_bo,
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.create_bo = gttX_create_bo, .name = "gttX" },
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{ .set_bo = gpu_set_bo, .cmp_bo = gpu_cmp_bo,
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.create_bo = gpu_create_bo, .name = "gpu" },
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{ .set_bo = gpu_set_bo, .cmp_bo = gpu_cmp_bo,
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.create_bo = gpuX_create_bo, .name = "gpuX" },
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void (*release_bo)(drm_intel_bo *bo);
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} access_modes[] = {
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{
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.name = "prw",
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.set_bo = prw_set_bo,
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.cmp_bo = prw_cmp_bo,
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.create_bo = unmapped_create_bo,
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.release_bo = nop_release_bo,
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},
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{
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.name = "cpu",
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.set_bo = cpu_set_bo,
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.cmp_bo = cpu_cmp_bo,
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.create_bo = unmapped_create_bo,
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.release_bo = nop_release_bo,
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},
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{
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.name = "gtt",
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.set_bo = gtt_set_bo,
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.cmp_bo = gtt_cmp_bo,
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.create_bo = gtt_create_bo,
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.release_bo = nop_release_bo,
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},
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{
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.name = "gttX",
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.set_bo = gtt_set_bo,
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.cmp_bo = gtt_cmp_bo,
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.create_bo = gttX_create_bo,
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.release_bo = nop_release_bo,
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},
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{
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.name = "wc",
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.set_bo = gtt_set_bo,
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.cmp_bo = gtt_cmp_bo,
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.create_bo = wc_create_bo,
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.release_bo = wc_release_bo,
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},
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{
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.name = "gpu",
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.set_bo = gpu_set_bo,
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.cmp_bo = gpu_cmp_bo,
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.create_bo = gpu_create_bo,
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.release_bo = nop_release_bo,
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},
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{
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.name = "gpuX",
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.set_bo = gpu_set_bo,
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.cmp_bo = gpu_cmp_bo,
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.create_bo = gpuX_create_bo,
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.release_bo = nop_release_bo,
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},
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};
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#define MAX_NUM_BUFFERS 1024
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@ -335,7 +398,63 @@ static void blt_copy_bo(drm_intel_bo *dst, drm_intel_bo *src)
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width, height, 32);
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}
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static void do_overwrite_source(struct access_mode *mode,
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static void cpu_copy_bo(drm_intel_bo *dst, drm_intel_bo *src)
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{
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const int size = width * height * sizeof(uint32_t);
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void *d, *s;
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gem_set_domain(fd, src->handle, I915_GEM_DOMAIN_CPU, 0);
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gem_set_domain(fd, dst->handle, I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
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s = gem_mmap__cpu(fd, src->handle, 0, size, PROT_READ);
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igt_assert(s != NULL);
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d = gem_mmap__cpu(fd, dst->handle, 0, size, PROT_WRITE);
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igt_assert(d != NULL);
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memcpy(d, s, size);
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munmap(d, size);
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munmap(s, size);
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}
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static void gtt_copy_bo(drm_intel_bo *dst, drm_intel_bo *src)
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{
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const int size = width * height * sizeof(uint32_t);
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void *d, *s;
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gem_set_domain(fd, src->handle, I915_GEM_DOMAIN_GTT, 0);
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gem_set_domain(fd, dst->handle, I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
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s = gem_mmap__gtt(fd, src->handle, size, PROT_READ);
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igt_assert(s != NULL);
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d = gem_mmap__gtt(fd, dst->handle, size, PROT_WRITE);
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igt_assert(d != NULL);
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memcpy(d, s, size);
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munmap(d, size);
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munmap(s, size);
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}
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static void wc_copy_bo(drm_intel_bo *dst, drm_intel_bo *src)
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{
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const int size = width * height * sizeof(uint32_t);
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void *d, *s;
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gem_set_domain(fd, src->handle, I915_GEM_DOMAIN_GTT, 0);
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gem_set_domain(fd, dst->handle, I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
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s = gem_mmap__wc(fd, src->handle, 0, size, PROT_READ);
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igt_assert(s != NULL);
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d = gem_mmap__wc(fd, dst->handle, 0, size, PROT_WRITE);
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igt_assert(d != NULL);
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memcpy(d, s, size);
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munmap(d, size);
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munmap(s, size);
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}
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static void do_overwrite_source(const struct access_mode *mode,
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drm_intel_bo **src, drm_intel_bo **dst,
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drm_intel_bo *dummy,
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do_copy do_copy_func)
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@ -355,7 +474,7 @@ static void do_overwrite_source(struct access_mode *mode,
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mode->cmp_bo(dst[i], i, width, height, dummy);
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}
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static void do_early_read(struct access_mode *mode,
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static void do_early_read(const struct access_mode *mode,
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drm_intel_bo **src, drm_intel_bo **dst,
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drm_intel_bo *dummy,
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do_copy do_copy_func)
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@ -371,7 +490,7 @@ static void do_early_read(struct access_mode *mode,
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mode->cmp_bo(dst[i], 0xdeadbeef, width, height, dummy);
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}
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static void do_gpu_read_after_write(struct access_mode *mode,
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static void do_gpu_read_after_write(const struct access_mode *mode,
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drm_intel_bo **src, drm_intel_bo **dst,
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drm_intel_bo *dummy,
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do_copy do_copy_func)
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@ -389,18 +508,18 @@ static void do_gpu_read_after_write(struct access_mode *mode,
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mode->cmp_bo(dst[i], 0xabcdabcd, width, height, dummy);
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}
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typedef void (*do_test)(struct access_mode *mode,
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typedef void (*do_test)(const struct access_mode *mode,
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drm_intel_bo **src, drm_intel_bo **dst,
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drm_intel_bo *dummy,
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do_copy do_copy_func);
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typedef void (*run_wrap)(struct access_mode *mode,
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typedef void (*run_wrap)(const struct access_mode *mode,
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drm_intel_bo **src, drm_intel_bo **dst,
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drm_intel_bo *dummy,
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do_test do_test_func,
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do_copy do_copy_func);
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static void run_single(struct access_mode *mode,
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static void run_single(const struct access_mode *mode,
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drm_intel_bo **src, drm_intel_bo **dst,
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drm_intel_bo *dummy,
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do_test do_test_func,
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@ -409,7 +528,7 @@ static void run_single(struct access_mode *mode,
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do_test_func(mode, src, dst, dummy, do_copy_func);
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}
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static void run_interruptible(struct access_mode *mode,
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static void run_interruptible(const struct access_mode *mode,
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drm_intel_bo **src, drm_intel_bo **dst,
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drm_intel_bo *dummy,
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do_test do_test_func,
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@ -421,37 +540,44 @@ static void run_interruptible(struct access_mode *mode,
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do_test_func(mode, src, dst, dummy, do_copy_func);
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}
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static void run_forked(struct access_mode *mode,
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static void run_forked(const struct access_mode *mode,
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drm_intel_bo **src, drm_intel_bo **dst,
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drm_intel_bo *dummy,
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do_test do_test_func,
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do_copy do_copy_func)
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{
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const int old_num_buffers = num_buffers;
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drm_intel_bufmgr *bufmgr;
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num_buffers /= 16;
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num_buffers += 2;
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igt_fork(child, 16) {
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drm_intel_bufmgr *bufmgr;
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/* recreate process local variables */
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bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
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drm_intel_bufmgr_gem_enable_reuse(bufmgr);
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batch = intel_batchbuffer_alloc(bufmgr, devid);
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for (int i = 0; i < num_buffers; i++) {
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src[i] = mode->create_bo(bufmgr, width, height);
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dst[i] = mode->create_bo(bufmgr, width, height);
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}
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dummy = mode->create_bo(bufmgr, width, height);
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for (int loop = 0; loop < 10; loop++)
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do_test_func(mode, src, dst, dummy, do_copy_func);
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/* as we borrow the fd, we need to reap our bo */
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for (int i = 0; i < num_buffers; i++) {
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drm_intel_bo_unreference(src[i]);
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drm_intel_bo_unreference(dst[i]);
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mode->release_bo(src[i]);
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mode->release_bo(dst[i]);
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}
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drm_intel_bo_unreference(dummy);
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mode->release_bo(dummy);
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intel_batchbuffer_free(batch);
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drm_intel_bufmgr_destroy(bufmgr);
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}
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@ -460,6 +586,40 @@ static void run_forked(struct access_mode *mode,
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num_buffers = old_num_buffers;
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}
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static void bit17_require(void)
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{
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struct drm_i915_gem_get_tiling2 {
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uint32_t handle;
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uint32_t tiling_mode;
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uint32_t swizzle_mode;
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uint32_t phys_swizzle_mode;
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} arg;
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#define DRM_IOCTL_I915_GEM_GET_TILING2 DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling2)
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memset(&arg, 0, sizeof(arg));
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arg.handle = gem_create(fd, 4096);
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gem_set_tiling(fd, arg.handle, I915_TILING_X, 512);
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do_or_die(drmIoctl(fd, DRM_IOCTL_I915_GEM_GET_TILING2, &arg));
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gem_close(fd, arg.handle);
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igt_require(arg.phys_swizzle_mode == arg.swizzle_mode);
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}
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static void cpu_require(void)
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{
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bit17_require();
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}
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static void gtt_require(void)
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{
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}
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static void wc_require(void)
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{
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bit17_require();
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igt_require_mmap_wc(fd);
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}
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static void bcs_require(void)
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{
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}
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@ -470,16 +630,19 @@ static void rcs_require(void)
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}
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static void
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run_basic_modes(struct access_mode *mode,
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run_basic_modes(const struct access_mode *mode,
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drm_intel_bo **src, drm_intel_bo **dst,
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drm_intel_bo *dummy, const char *suffix,
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run_wrap run_wrap_func)
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{
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struct {
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const struct {
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const char *prefix;
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do_copy copy;
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void (*require)(void);
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} pipelines[] = {
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{ "cpu", cpu_copy_bo, cpu_require },
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{ "gtt", gtt_copy_bo, gtt_require },
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{ "wc", wc_copy_bo, wc_require },
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{ "bcs", blt_copy_bo, bcs_require },
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{ "rcs", render_copy_bo, rcs_require },
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{ NULL, NULL }
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@ -510,7 +673,7 @@ run_basic_modes(struct access_mode *mode,
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}
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static void
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run_modes(struct access_mode *mode)
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run_modes(const struct access_mode *mode)
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{
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drm_intel_bo *src[MAX_NUM_BUFFERS], *dst[MAX_NUM_BUFFERS], *dummy = NULL;
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drm_intel_bufmgr *bufmgr;
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@ -535,10 +698,10 @@ run_modes(struct access_mode *mode)
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igt_fixture {
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for (int i = 0; i < num_buffers; i++) {
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drm_intel_bo_unreference(src[i]);
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drm_intel_bo_unreference(dst[i]);
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mode->release_bo(src[i]);
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mode->release_bo(dst[i]);
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}
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drm_intel_bo_unreference(dummy);
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mode->release_bo(dummy);
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intel_batchbuffer_free(batch);
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drm_intel_bufmgr_destroy(bufmgr);
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}
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