mirror of
https://github.com/tiagovignatti/intel-gpu-tools.git
synced 2026-08-19 04:13:01 +00:00
lib: extract rendercopy functions from gem_stress
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Daniel Vetter
+7
-1
@@ -21,5 +21,11 @@ libintel_tools_la_SOURCES = \
|
||||
intel_mmio.c \
|
||||
intel_pci.c \
|
||||
intel_reg.h \
|
||||
intel_reg_map.c
|
||||
gem_stress_i915.c \
|
||||
gem_stress_i830.c \
|
||||
gen6_render.h \
|
||||
gem_stress_gen6.c \
|
||||
intel_reg_map.c \
|
||||
gem_stress.h \
|
||||
$(NULL)
|
||||
|
||||
|
||||
@@ -0,0 +1,599 @@
|
||||
#include "rendercopy.h"
|
||||
#include "gen6_render.h"
|
||||
|
||||
#include <assert.h>
|
||||
|
||||
#define ALIGN(x, y) (((x) + (y)-1) & ~((y)-1))
|
||||
#define VERTEX_SIZE (3*4)
|
||||
|
||||
static const uint32_t ps_kernel_nomask_affine[][4] = {
|
||||
{ 0x0060005a, 0x204077be, 0x000000c0, 0x008d0040 },
|
||||
{ 0x0060005a, 0x206077be, 0x000000c0, 0x008d0080 },
|
||||
{ 0x0060005a, 0x208077be, 0x000000d0, 0x008d0040 },
|
||||
{ 0x0060005a, 0x20a077be, 0x000000d0, 0x008d0080 },
|
||||
{ 0x00000201, 0x20080061, 0x00000000, 0x00000000 },
|
||||
{ 0x00600001, 0x20200022, 0x008d0000, 0x00000000 },
|
||||
{ 0x02800031, 0x21c01cc9, 0x00000020, 0x0a8a0001 },
|
||||
{ 0x00600001, 0x204003be, 0x008d01c0, 0x00000000 },
|
||||
{ 0x00600001, 0x206003be, 0x008d01e0, 0x00000000 },
|
||||
{ 0x00600001, 0x208003be, 0x008d0200, 0x00000000 },
|
||||
{ 0x00600001, 0x20a003be, 0x008d0220, 0x00000000 },
|
||||
{ 0x00600001, 0x20c003be, 0x008d0240, 0x00000000 },
|
||||
{ 0x00600001, 0x20e003be, 0x008d0260, 0x00000000 },
|
||||
{ 0x00600001, 0x210003be, 0x008d0280, 0x00000000 },
|
||||
{ 0x00600001, 0x212003be, 0x008d02a0, 0x00000000 },
|
||||
{ 0x05800031, 0x24001cc8, 0x00000040, 0x90019000 },
|
||||
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
|
||||
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
|
||||
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
|
||||
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
|
||||
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
|
||||
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
|
||||
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
|
||||
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
|
||||
};
|
||||
|
||||
static uint32_t
|
||||
batch_used(struct intel_batchbuffer *batch)
|
||||
{
|
||||
return batch->ptr - batch->buffer;
|
||||
}
|
||||
|
||||
static uint32_t
|
||||
batch_align(struct intel_batchbuffer *batch, uint32_t align)
|
||||
{
|
||||
uint32_t offset = batch_used(batch);
|
||||
offset = ALIGN(offset, align);
|
||||
batch->ptr = batch->buffer + offset;
|
||||
return offset;
|
||||
}
|
||||
|
||||
static uint32_t
|
||||
batch_round_upto(struct intel_batchbuffer *batch, uint32_t divisor)
|
||||
{
|
||||
uint32_t offset = batch_used(batch);
|
||||
offset = (offset + divisor-1) / divisor * divisor;
|
||||
batch->ptr = batch->buffer + offset;
|
||||
return offset;
|
||||
}
|
||||
|
||||
static void *
|
||||
batch_alloc(struct intel_batchbuffer *batch, uint32_t size, uint32_t align)
|
||||
{
|
||||
uint32_t offset = batch_align(batch, align);
|
||||
batch->ptr += size;
|
||||
return memset(batch->buffer + offset, 0, size);
|
||||
}
|
||||
|
||||
static uint32_t
|
||||
batch_offset(struct intel_batchbuffer *batch, void *ptr)
|
||||
{
|
||||
return (uint8_t *)ptr - batch->buffer;
|
||||
}
|
||||
|
||||
static uint32_t
|
||||
batch_copy(struct intel_batchbuffer *batch, const void *ptr, uint32_t size, uint32_t align)
|
||||
{
|
||||
return batch_offset(batch, memcpy(batch_alloc(batch, size, align), ptr, size));
|
||||
}
|
||||
|
||||
static void
|
||||
gen6_render_flush(struct intel_batchbuffer *batch, uint32_t batch_end)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = drm_intel_bo_subdata(batch->bo, 0, 4096, batch->buffer);
|
||||
if (ret == 0)
|
||||
ret = drm_intel_bo_mrb_exec(batch->bo, batch_end,
|
||||
NULL, 0, 0, 0);
|
||||
assert(ret == 0);
|
||||
}
|
||||
|
||||
static uint32_t
|
||||
gen6_bind_buf(struct intel_batchbuffer *batch, struct scratch_buf *buf,
|
||||
uint32_t format, int is_dst)
|
||||
{
|
||||
struct gen6_surface_state *ss;
|
||||
uint32_t write_domain, read_domain;
|
||||
int ret;
|
||||
|
||||
if (is_dst) {
|
||||
write_domain = read_domain = I915_GEM_DOMAIN_RENDER;
|
||||
} else {
|
||||
write_domain = 0;
|
||||
read_domain = I915_GEM_DOMAIN_SAMPLER;
|
||||
}
|
||||
|
||||
ss = batch_alloc(batch, sizeof(*ss), 32);
|
||||
ss->ss0.surface_type = GEN6_SURFACE_2D;
|
||||
ss->ss0.surface_format = format;
|
||||
|
||||
ss->ss0.data_return_format = GEN6_SURFACERETURNFORMAT_FLOAT32;
|
||||
ss->ss0.color_blend = 1;
|
||||
ss->ss1.base_addr = buf->bo->offset;
|
||||
|
||||
ret = drm_intel_bo_emit_reloc(batch->bo,
|
||||
batch_offset(batch, ss) + 4,
|
||||
buf->bo, 0,
|
||||
read_domain, write_domain);
|
||||
assert(ret == 0);
|
||||
|
||||
ss->ss2.height = buf_height(buf) - 1;
|
||||
ss->ss2.width = buf_width(buf) - 1;
|
||||
ss->ss3.pitch = buf->stride - 1;
|
||||
ss->ss3.tiled_surface = buf->tiling != I915_TILING_NONE;
|
||||
ss->ss3.tile_walk = buf->tiling == I915_TILING_Y;
|
||||
|
||||
return batch_offset(batch, ss);
|
||||
}
|
||||
|
||||
static uint32_t
|
||||
gen6_bind_surfaces(struct intel_batchbuffer *batch,
|
||||
struct scratch_buf *src,
|
||||
struct scratch_buf *dst)
|
||||
{
|
||||
uint32_t *binding_table;
|
||||
|
||||
binding_table = batch_alloc(batch, 32, 32);
|
||||
|
||||
binding_table[0] =
|
||||
gen6_bind_buf(batch, dst, GEN6_SURFACEFORMAT_B8G8R8A8_UNORM, 1);
|
||||
binding_table[1] =
|
||||
gen6_bind_buf(batch, src, GEN6_SURFACEFORMAT_B8G8R8A8_UNORM, 0);
|
||||
|
||||
return batch_offset(batch, binding_table);
|
||||
}
|
||||
|
||||
static void
|
||||
gen6_emit_sip(struct intel_batchbuffer *batch)
|
||||
{
|
||||
OUT_BATCH(GEN6_STATE_SIP | 0);
|
||||
OUT_BATCH(0);
|
||||
}
|
||||
|
||||
static void
|
||||
gen6_emit_urb(struct intel_batchbuffer *batch)
|
||||
{
|
||||
OUT_BATCH(GEN6_3DSTATE_URB | (3 - 2));
|
||||
OUT_BATCH((1 - 1) << GEN6_3DSTATE_URB_VS_SIZE_SHIFT |
|
||||
24 << GEN6_3DSTATE_URB_VS_ENTRIES_SHIFT); /* at least 24 on GEN6 */
|
||||
OUT_BATCH(0 << GEN6_3DSTATE_URB_GS_SIZE_SHIFT |
|
||||
0 << GEN6_3DSTATE_URB_GS_ENTRIES_SHIFT); /* no GS thread */
|
||||
}
|
||||
|
||||
static void
|
||||
gen6_emit_state_base_address(struct intel_batchbuffer *batch)
|
||||
{
|
||||
OUT_BATCH(GEN6_STATE_BASE_ADDRESS | (10 - 2));
|
||||
OUT_BATCH(0); /* general */
|
||||
OUT_RELOC(batch->bo, /* surface */
|
||||
I915_GEM_DOMAIN_INSTRUCTION, 0,
|
||||
BASE_ADDRESS_MODIFY);
|
||||
OUT_RELOC(batch->bo, /* instruction */
|
||||
I915_GEM_DOMAIN_INSTRUCTION, 0,
|
||||
BASE_ADDRESS_MODIFY);
|
||||
OUT_BATCH(0); /* indirect */
|
||||
OUT_RELOC(batch->bo, /* dynamic */
|
||||
I915_GEM_DOMAIN_INSTRUCTION, 0,
|
||||
BASE_ADDRESS_MODIFY);
|
||||
|
||||
/* upper bounds, disable */
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(BASE_ADDRESS_MODIFY);
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(BASE_ADDRESS_MODIFY);
|
||||
}
|
||||
|
||||
static void
|
||||
gen6_emit_viewports(struct intel_batchbuffer *batch, uint32_t cc_vp)
|
||||
{
|
||||
OUT_BATCH(GEN6_3DSTATE_VIEWPORT_STATE_POINTERS |
|
||||
GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_CC |
|
||||
(4 - 2));
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(cc_vp);
|
||||
}
|
||||
|
||||
static void
|
||||
gen6_emit_vs(struct intel_batchbuffer *batch)
|
||||
{
|
||||
/* disable VS constant buffer */
|
||||
OUT_BATCH(GEN6_3DSTATE_CONSTANT_VS | (5 - 2));
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(0);
|
||||
|
||||
OUT_BATCH(GEN6_3DSTATE_VS | (6 - 2));
|
||||
OUT_BATCH(0); /* no VS kernel */
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(0); /* pass-through */
|
||||
}
|
||||
|
||||
static void
|
||||
gen6_emit_gs(struct intel_batchbuffer *batch)
|
||||
{
|
||||
/* disable GS constant buffer */
|
||||
OUT_BATCH(GEN6_3DSTATE_CONSTANT_GS | (5 - 2));
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(0);
|
||||
|
||||
OUT_BATCH(GEN6_3DSTATE_GS | (7 - 2));
|
||||
OUT_BATCH(0); /* no GS kernel */
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(0); /* pass-through */
|
||||
}
|
||||
|
||||
static void
|
||||
gen6_emit_clip(struct intel_batchbuffer *batch)
|
||||
{
|
||||
OUT_BATCH(GEN6_3DSTATE_CLIP | (4 - 2));
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(0); /* pass-through */
|
||||
OUT_BATCH(0);
|
||||
}
|
||||
|
||||
static void
|
||||
gen6_emit_wm_constants(struct intel_batchbuffer *batch)
|
||||
{
|
||||
/* disable WM constant buffer */
|
||||
OUT_BATCH(GEN6_3DSTATE_CONSTANT_PS | (5 - 2));
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(0);
|
||||
}
|
||||
|
||||
static void
|
||||
gen6_emit_null_depth_buffer(struct intel_batchbuffer *batch)
|
||||
{
|
||||
OUT_BATCH(GEN6_3DSTATE_DEPTH_BUFFER | (7 - 2));
|
||||
OUT_BATCH(GEN6_SURFACE_NULL << GEN6_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT |
|
||||
GEN6_DEPTHFORMAT_D32_FLOAT << GEN6_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT);
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(0);
|
||||
|
||||
OUT_BATCH(GEN6_3DSTATE_CLEAR_PARAMS | (2 - 2));
|
||||
OUT_BATCH(0);
|
||||
}
|
||||
|
||||
static void
|
||||
gen6_emit_invariant(struct intel_batchbuffer *batch)
|
||||
{
|
||||
OUT_BATCH(GEN6_PIPELINE_SELECT | PIPELINE_SELECT_3D);
|
||||
|
||||
OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE | (3 - 2));
|
||||
OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER |
|
||||
GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_1); /* 1 sample/pixel */
|
||||
OUT_BATCH(0);
|
||||
|
||||
OUT_BATCH(GEN6_3DSTATE_SAMPLE_MASK | (2 - 2));
|
||||
OUT_BATCH(1);
|
||||
}
|
||||
|
||||
static void
|
||||
gen6_emit_cc(struct intel_batchbuffer *batch, uint32_t blend)
|
||||
{
|
||||
OUT_BATCH(GEN6_3DSTATE_CC_STATE_POINTERS | (4 - 2));
|
||||
OUT_BATCH(blend | 1);
|
||||
OUT_BATCH(1024 | 1);
|
||||
OUT_BATCH(1024 | 1);
|
||||
}
|
||||
|
||||
static void
|
||||
gen6_emit_sampler(struct intel_batchbuffer *batch, uint32_t state)
|
||||
{
|
||||
OUT_BATCH(GEN6_3DSTATE_SAMPLER_STATE_POINTERS |
|
||||
GEN6_3DSTATE_SAMPLER_STATE_MODIFY_PS |
|
||||
(4 - 2));
|
||||
OUT_BATCH(0); /* VS */
|
||||
OUT_BATCH(0); /* GS */
|
||||
OUT_BATCH(state);
|
||||
}
|
||||
|
||||
static void
|
||||
gen6_emit_sf(struct intel_batchbuffer *batch)
|
||||
{
|
||||
OUT_BATCH(GEN6_3DSTATE_SF | (20 - 2));
|
||||
OUT_BATCH(1 << GEN6_3DSTATE_SF_NUM_OUTPUTS_SHIFT |
|
||||
1 << GEN6_3DSTATE_SF_URB_ENTRY_READ_LENGTH_SHIFT |
|
||||
1 << GEN6_3DSTATE_SF_URB_ENTRY_READ_OFFSET_SHIFT);
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(GEN6_3DSTATE_SF_CULL_NONE);
|
||||
OUT_BATCH(2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT); /* DW4 */
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(0); /* DW9 */
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(0); /* DW14 */
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(0); /* DW19 */
|
||||
}
|
||||
|
||||
static void
|
||||
gen6_emit_wm(struct intel_batchbuffer *batch, int kernel)
|
||||
{
|
||||
OUT_BATCH(GEN6_3DSTATE_WM | (9 - 2));
|
||||
OUT_BATCH(kernel);
|
||||
OUT_BATCH(1 << GEN6_3DSTATE_WM_SAMPLER_COUNT_SHIFT |
|
||||
2 << GEN6_3DSTATE_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT);
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(6 << GEN6_3DSTATE_WM_DISPATCH_START_GRF_0_SHIFT); /* DW4 */
|
||||
OUT_BATCH((40 - 1) << GEN6_3DSTATE_WM_MAX_THREADS_SHIFT |
|
||||
GEN6_3DSTATE_WM_DISPATCH_ENABLE |
|
||||
GEN6_3DSTATE_WM_16_DISPATCH_ENABLE);
|
||||
OUT_BATCH(1 << GEN6_3DSTATE_WM_NUM_SF_OUTPUTS_SHIFT |
|
||||
GEN6_3DSTATE_WM_PERSPECTIVE_PIXEL_BARYCENTRIC);
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(0);
|
||||
}
|
||||
|
||||
static void
|
||||
gen6_emit_binding_table(struct intel_batchbuffer *batch, uint32_t wm_table)
|
||||
{
|
||||
OUT_BATCH(GEN6_3DSTATE_BINDING_TABLE_POINTERS |
|
||||
GEN6_3DSTATE_BINDING_TABLE_MODIFY_PS |
|
||||
(4 - 2));
|
||||
OUT_BATCH(0); /* vs */
|
||||
OUT_BATCH(0); /* gs */
|
||||
OUT_BATCH(wm_table);
|
||||
}
|
||||
|
||||
static void
|
||||
gen6_emit_drawing_rectangle(struct intel_batchbuffer *batch, struct scratch_buf *dst)
|
||||
{
|
||||
OUT_BATCH(GEN6_3DSTATE_DRAWING_RECTANGLE | (4 - 2));
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH((buf_height(dst) - 1) << 16 | (buf_width(dst) - 1));
|
||||
OUT_BATCH(0);
|
||||
}
|
||||
|
||||
static void
|
||||
gen6_emit_vertex_elements(struct intel_batchbuffer *batch)
|
||||
{
|
||||
/* The VUE layout
|
||||
* dword 0-3: pad (0.0, 0.0, 0.0. 0.0)
|
||||
* dword 4-7: position (x, y, 1.0, 1.0),
|
||||
* dword 8-11: texture coordinate 0 (u0, v0, 0, 0)
|
||||
*
|
||||
* dword 4-11 are fetched from vertex buffer
|
||||
*/
|
||||
OUT_BATCH(GEN6_3DSTATE_VERTEX_ELEMENTS | (2 * 3 + 1 - 2));
|
||||
|
||||
OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
|
||||
GEN6_SURFACEFORMAT_R32G32B32A32_FLOAT << VE0_FORMAT_SHIFT |
|
||||
0 << VE0_OFFSET_SHIFT);
|
||||
OUT_BATCH(GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT |
|
||||
GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT |
|
||||
GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
|
||||
GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT);
|
||||
|
||||
/* x,y */
|
||||
OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
|
||||
GEN6_SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT |
|
||||
0 << VE0_OFFSET_SHIFT); /* offsets vb in bytes */
|
||||
OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
|
||||
GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
|
||||
GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT |
|
||||
GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT);
|
||||
|
||||
/* u0, v0 */
|
||||
OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
|
||||
GEN6_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT |
|
||||
4 << VE0_OFFSET_SHIFT); /* offset vb in bytes */
|
||||
OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
|
||||
GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
|
||||
GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
|
||||
GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT);
|
||||
}
|
||||
|
||||
static uint32_t
|
||||
gen6_create_cc_viewport(struct intel_batchbuffer *batch)
|
||||
{
|
||||
struct gen6_cc_viewport *vp;
|
||||
|
||||
vp = batch_alloc(batch, sizeof(*vp), 32);
|
||||
|
||||
vp->min_depth = -1.e35;
|
||||
vp->max_depth = 1.e35;
|
||||
|
||||
return batch_offset(batch, vp);
|
||||
}
|
||||
|
||||
static uint32_t
|
||||
gen6_create_cc_blend(struct intel_batchbuffer *batch)
|
||||
{
|
||||
struct gen6_blend_state *blend;
|
||||
|
||||
blend = batch_alloc(batch, sizeof(*blend), 64);
|
||||
|
||||
blend->blend0.dest_blend_factor = GEN6_BLENDFACTOR_ZERO;
|
||||
blend->blend0.source_blend_factor = GEN6_BLENDFACTOR_ONE;
|
||||
blend->blend0.blend_func = GEN6_BLENDFUNCTION_ADD;
|
||||
blend->blend0.blend_enable = 1;
|
||||
|
||||
blend->blend1.post_blend_clamp_enable = 1;
|
||||
blend->blend1.pre_blend_clamp_enable = 1;
|
||||
|
||||
return batch_offset(batch, blend);
|
||||
}
|
||||
|
||||
static uint32_t
|
||||
gen6_create_kernel(struct intel_batchbuffer *batch)
|
||||
{
|
||||
return batch_copy(batch, ps_kernel_nomask_affine,
|
||||
sizeof(ps_kernel_nomask_affine),
|
||||
64);
|
||||
}
|
||||
|
||||
static uint32_t
|
||||
gen6_create_sampler(struct intel_batchbuffer *batch,
|
||||
sampler_filter_t filter,
|
||||
sampler_extend_t extend)
|
||||
{
|
||||
struct gen6_sampler_state *ss;
|
||||
|
||||
ss = batch_alloc(batch, sizeof(*ss), 32);
|
||||
ss->ss0.lod_preclamp = 1; /* GL mode */
|
||||
|
||||
/* We use the legacy mode to get the semantics specified by
|
||||
* the Render extension. */
|
||||
ss->ss0.border_color_mode = GEN6_BORDER_COLOR_MODE_LEGACY;
|
||||
|
||||
switch (filter) {
|
||||
default:
|
||||
case SAMPLER_FILTER_NEAREST:
|
||||
ss->ss0.min_filter = GEN6_MAPFILTER_NEAREST;
|
||||
ss->ss0.mag_filter = GEN6_MAPFILTER_NEAREST;
|
||||
break;
|
||||
case SAMPLER_FILTER_BILINEAR:
|
||||
ss->ss0.min_filter = GEN6_MAPFILTER_LINEAR;
|
||||
ss->ss0.mag_filter = GEN6_MAPFILTER_LINEAR;
|
||||
break;
|
||||
}
|
||||
|
||||
switch (extend) {
|
||||
default:
|
||||
case SAMPLER_EXTEND_NONE:
|
||||
ss->ss1.r_wrap_mode = GEN6_TEXCOORDMODE_CLAMP_BORDER;
|
||||
ss->ss1.s_wrap_mode = GEN6_TEXCOORDMODE_CLAMP_BORDER;
|
||||
ss->ss1.t_wrap_mode = GEN6_TEXCOORDMODE_CLAMP_BORDER;
|
||||
break;
|
||||
case SAMPLER_EXTEND_REPEAT:
|
||||
ss->ss1.r_wrap_mode = GEN6_TEXCOORDMODE_WRAP;
|
||||
ss->ss1.s_wrap_mode = GEN6_TEXCOORDMODE_WRAP;
|
||||
ss->ss1.t_wrap_mode = GEN6_TEXCOORDMODE_WRAP;
|
||||
break;
|
||||
case SAMPLER_EXTEND_PAD:
|
||||
ss->ss1.r_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
|
||||
ss->ss1.s_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
|
||||
ss->ss1.t_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
|
||||
break;
|
||||
case SAMPLER_EXTEND_REFLECT:
|
||||
ss->ss1.r_wrap_mode = GEN6_TEXCOORDMODE_MIRROR;
|
||||
ss->ss1.s_wrap_mode = GEN6_TEXCOORDMODE_MIRROR;
|
||||
ss->ss1.t_wrap_mode = GEN6_TEXCOORDMODE_MIRROR;
|
||||
break;
|
||||
}
|
||||
|
||||
return batch_offset(batch, ss);
|
||||
}
|
||||
|
||||
static void gen6_emit_vertex_buffer(struct intel_batchbuffer *batch)
|
||||
{
|
||||
OUT_BATCH(GEN6_3DSTATE_VERTEX_BUFFERS | 3);
|
||||
OUT_BATCH(VB0_VERTEXDATA |
|
||||
0 << VB0_BUFFER_INDEX_SHIFT |
|
||||
VERTEX_SIZE << VB0_BUFFER_PITCH_SHIFT);
|
||||
OUT_RELOC(batch->bo, I915_GEM_DOMAIN_VERTEX, 0, 0);
|
||||
OUT_RELOC(batch->bo, I915_GEM_DOMAIN_VERTEX, 0, batch->bo->size-1);
|
||||
OUT_BATCH(0);
|
||||
}
|
||||
|
||||
static uint32_t gen6_emit_primitive(struct intel_batchbuffer *batch)
|
||||
{
|
||||
uint32_t offset;
|
||||
|
||||
OUT_BATCH(GEN6_3DPRIMITIVE |
|
||||
GEN6_3DPRIMITIVE_VERTEX_SEQUENTIAL |
|
||||
_3DPRIM_RECTLIST << GEN6_3DPRIMITIVE_TOPOLOGY_SHIFT |
|
||||
0 << 9 |
|
||||
4);
|
||||
OUT_BATCH(3); /* vertex count */
|
||||
offset = batch_used(batch);
|
||||
OUT_BATCH(0); /* vertex_index */
|
||||
OUT_BATCH(1); /* single instance */
|
||||
OUT_BATCH(0); /* start instance location */
|
||||
OUT_BATCH(0); /* index buffer offset, ignored */
|
||||
|
||||
return offset;
|
||||
}
|
||||
|
||||
void gen6_render_copyfunc(struct intel_batchbuffer *batch,
|
||||
struct scratch_buf *src, unsigned src_x, unsigned src_y,
|
||||
unsigned width, unsigned height,
|
||||
struct scratch_buf *dst, unsigned dst_x, unsigned dst_y)
|
||||
{
|
||||
uint32_t wm_state, wm_kernel, wm_table;
|
||||
uint32_t cc_vp, cc_blend, offset;
|
||||
uint32_t batch_end;
|
||||
|
||||
intel_batchbuffer_flush(batch);
|
||||
|
||||
batch->ptr = batch->buffer + 1024;
|
||||
batch_alloc(batch, 64, 64);
|
||||
wm_table = gen6_bind_surfaces(batch, src, dst);
|
||||
wm_kernel = gen6_create_kernel(batch);
|
||||
wm_state = gen6_create_sampler(batch,
|
||||
SAMPLER_FILTER_NEAREST,
|
||||
SAMPLER_EXTEND_NONE);
|
||||
|
||||
cc_vp = gen6_create_cc_viewport(batch);
|
||||
cc_blend = gen6_create_cc_blend(batch);
|
||||
|
||||
batch->ptr = batch->buffer;
|
||||
|
||||
gen6_emit_invariant(batch);
|
||||
gen6_emit_state_base_address(batch);
|
||||
|
||||
gen6_emit_sip(batch);
|
||||
gen6_emit_urb(batch);
|
||||
|
||||
gen6_emit_viewports(batch, cc_vp);
|
||||
gen6_emit_vs(batch);
|
||||
gen6_emit_gs(batch);
|
||||
gen6_emit_clip(batch);
|
||||
gen6_emit_wm_constants(batch);
|
||||
gen6_emit_null_depth_buffer(batch);
|
||||
|
||||
gen6_emit_drawing_rectangle(batch, dst);
|
||||
gen6_emit_cc(batch, cc_blend);
|
||||
gen6_emit_sampler(batch, wm_state);
|
||||
gen6_emit_sf(batch);
|
||||
gen6_emit_wm(batch, wm_kernel);
|
||||
gen6_emit_vertex_elements(batch);
|
||||
gen6_emit_binding_table(batch, wm_table);
|
||||
|
||||
gen6_emit_vertex_buffer(batch);
|
||||
offset = gen6_emit_primitive(batch);
|
||||
|
||||
OUT_BATCH(MI_BATCH_BUFFER_END);
|
||||
batch_end = batch_align(batch, 8);
|
||||
|
||||
*(uint32_t*)(batch->buffer + offset) =
|
||||
batch_round_upto(batch, VERTEX_SIZE)/VERTEX_SIZE;
|
||||
|
||||
emit_vertex_2s(batch, dst_x + width, dst_y + height);
|
||||
emit_vertex_normalized(batch, src_x + width, buf_width(src));
|
||||
emit_vertex_normalized(batch, src_y + height, buf_height(src));
|
||||
|
||||
emit_vertex_2s(batch, dst_x, dst_y + height);
|
||||
emit_vertex_normalized(batch, src_x, buf_width(src));
|
||||
emit_vertex_normalized(batch, src_y + height, buf_height(src));
|
||||
|
||||
emit_vertex_2s(batch, dst_x, dst_y);
|
||||
emit_vertex_normalized(batch, src_x, buf_width(src));
|
||||
emit_vertex_normalized(batch, src_y, buf_height(src));
|
||||
|
||||
gen6_render_flush(batch, batch_end);
|
||||
intel_batchbuffer_reset(batch);
|
||||
}
|
||||
@@ -0,0 +1,344 @@
|
||||
#include "i830_reg.h"
|
||||
#include "rendercopy.h"
|
||||
|
||||
#define TB0C_LAST_STAGE (1 << 31)
|
||||
#define TB0C_RESULT_SCALE_1X (0 << 29)
|
||||
#define TB0C_RESULT_SCALE_2X (1 << 29)
|
||||
#define TB0C_RESULT_SCALE_4X (2 << 29)
|
||||
#define TB0C_OP_MODULE (3 << 25)
|
||||
#define TB0C_OUTPUT_WRITE_CURRENT (0 << 24)
|
||||
#define TB0C_OUTPUT_WRITE_ACCUM (1 << 24)
|
||||
#define TB0C_ARG3_REPLICATE_ALPHA (1<<23)
|
||||
#define TB0C_ARG3_INVERT (1<<22)
|
||||
#define TB0C_ARG3_SEL_XXX
|
||||
#define TB0C_ARG2_REPLICATE_ALPHA (1<<17)
|
||||
#define TB0C_ARG2_INVERT (1<<16)
|
||||
#define TB0C_ARG2_SEL_ONE (0 << 12)
|
||||
#define TB0C_ARG2_SEL_FACTOR (1 << 12)
|
||||
#define TB0C_ARG2_SEL_TEXEL0 (6 << 12)
|
||||
#define TB0C_ARG2_SEL_TEXEL1 (7 << 12)
|
||||
#define TB0C_ARG2_SEL_TEXEL2 (8 << 12)
|
||||
#define TB0C_ARG2_SEL_TEXEL3 (9 << 12)
|
||||
#define TB0C_ARG1_REPLICATE_ALPHA (1<<11)
|
||||
#define TB0C_ARG1_INVERT (1<<10)
|
||||
#define TB0C_ARG1_SEL_ONE (0 << 6)
|
||||
#define TB0C_ARG1_SEL_TEXEL0 (6 << 6)
|
||||
#define TB0C_ARG1_SEL_TEXEL1 (7 << 6)
|
||||
#define TB0C_ARG1_SEL_TEXEL2 (8 << 6)
|
||||
#define TB0C_ARG1_SEL_TEXEL3 (9 << 6)
|
||||
#define TB0C_ARG0_REPLICATE_ALPHA (1<<5)
|
||||
#define TB0C_ARG0_SEL_XXX
|
||||
|
||||
#define TB0A_CTR_STAGE_ENABLE (1<<31)
|
||||
#define TB0A_RESULT_SCALE_1X (0 << 29)
|
||||
#define TB0A_RESULT_SCALE_2X (1 << 29)
|
||||
#define TB0A_RESULT_SCALE_4X (2 << 29)
|
||||
#define TB0A_OP_MODULE (3 << 25)
|
||||
#define TB0A_OUTPUT_WRITE_CURRENT (0<<24)
|
||||
#define TB0A_OUTPUT_WRITE_ACCUM (1<<24)
|
||||
#define TB0A_CTR_STAGE_SEL_BITS_XXX
|
||||
#define TB0A_ARG3_SEL_XXX
|
||||
#define TB0A_ARG3_INVERT (1<<17)
|
||||
#define TB0A_ARG2_INVERT (1<<16)
|
||||
#define TB0A_ARG2_SEL_ONE (0 << 12)
|
||||
#define TB0A_ARG2_SEL_TEXEL0 (6 << 12)
|
||||
#define TB0A_ARG2_SEL_TEXEL1 (7 << 12)
|
||||
#define TB0A_ARG2_SEL_TEXEL2 (8 << 12)
|
||||
#define TB0A_ARG2_SEL_TEXEL3 (9 << 12)
|
||||
#define TB0A_ARG1_INVERT (1<<10)
|
||||
#define TB0A_ARG1_SEL_ONE (0 << 6)
|
||||
#define TB0A_ARG1_SEL_TEXEL0 (6 << 6)
|
||||
#define TB0A_ARG1_SEL_TEXEL1 (7 << 6)
|
||||
#define TB0A_ARG1_SEL_TEXEL2 (8 << 6)
|
||||
#define TB0A_ARG1_SEL_TEXEL3 (9 << 6)
|
||||
|
||||
void gen2_render_copyfunc(struct intel_batchbuffer *batch,
|
||||
struct scratch_buf *src, unsigned src_x, unsigned src_y,
|
||||
unsigned width, unsigned height,
|
||||
struct scratch_buf *dst, unsigned dst_x, unsigned dst_y)
|
||||
{
|
||||
/* invariant state */
|
||||
{
|
||||
OUT_BATCH(_3DSTATE_MAP_CUBE | MAP_UNIT(0));
|
||||
OUT_BATCH(_3DSTATE_MAP_CUBE | MAP_UNIT(1));
|
||||
OUT_BATCH(_3DSTATE_MAP_CUBE | MAP_UNIT(2));
|
||||
OUT_BATCH(_3DSTATE_MAP_CUBE | MAP_UNIT(3));
|
||||
|
||||
OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
|
||||
OUT_BATCH(0);
|
||||
|
||||
OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
|
||||
OUT_BATCH(0);
|
||||
|
||||
OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
|
||||
OUT_BATCH(0);
|
||||
|
||||
OUT_BATCH(_3DSTATE_FOG_MODE_CMD);
|
||||
OUT_BATCH(FOGFUNC_ENABLE |
|
||||
FOG_LINEAR_CONST | FOGSRC_INDEX_Z | ENABLE_FOG_DENSITY);
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(0);
|
||||
|
||||
OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD |
|
||||
MAP_UNIT(0) |
|
||||
DISABLE_TEX_STREAM_BUMP |
|
||||
ENABLE_TEX_STREAM_COORD_SET |
|
||||
TEX_STREAM_COORD_SET(0) |
|
||||
ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(0));
|
||||
OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD |
|
||||
MAP_UNIT(1) |
|
||||
DISABLE_TEX_STREAM_BUMP |
|
||||
ENABLE_TEX_STREAM_COORD_SET |
|
||||
TEX_STREAM_COORD_SET(1) |
|
||||
ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(1));
|
||||
OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD |
|
||||
MAP_UNIT(2) |
|
||||
DISABLE_TEX_STREAM_BUMP |
|
||||
ENABLE_TEX_STREAM_COORD_SET |
|
||||
TEX_STREAM_COORD_SET(2) |
|
||||
ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(2));
|
||||
OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD |
|
||||
MAP_UNIT(3) |
|
||||
DISABLE_TEX_STREAM_BUMP |
|
||||
ENABLE_TEX_STREAM_COORD_SET |
|
||||
TEX_STREAM_COORD_SET(3) |
|
||||
ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(3));
|
||||
|
||||
OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
|
||||
OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(0));
|
||||
OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
|
||||
OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(1));
|
||||
OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
|
||||
OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(2));
|
||||
OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
|
||||
OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(3));
|
||||
|
||||
OUT_BATCH(_3DSTATE_RASTER_RULES_CMD |
|
||||
ENABLE_POINT_RASTER_RULE |
|
||||
OGL_POINT_RASTER_RULE |
|
||||
ENABLE_LINE_STRIP_PROVOKE_VRTX |
|
||||
ENABLE_TRI_FAN_PROVOKE_VRTX |
|
||||
ENABLE_TRI_STRIP_PROVOKE_VRTX |
|
||||
LINE_STRIP_PROVOKE_VRTX(1) |
|
||||
TRI_FAN_PROVOKE_VRTX(2) | TRI_STRIP_PROVOKE_VRTX(2));
|
||||
|
||||
OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
|
||||
|
||||
OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD);
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(0);
|
||||
|
||||
OUT_BATCH(_3DSTATE_VERTEX_TRANSFORM);
|
||||
OUT_BATCH(DISABLE_VIEWPORT_TRANSFORM | DISABLE_PERSPECTIVE_DIVIDE);
|
||||
|
||||
OUT_BATCH(_3DSTATE_W_STATE_CMD);
|
||||
OUT_BATCH(MAGIC_W_STATE_DWORD1);
|
||||
OUT_BATCH(0x3f800000 /* 1.0 in IEEE float */ );
|
||||
|
||||
OUT_BATCH(_3DSTATE_COLOR_FACTOR_CMD);
|
||||
OUT_BATCH(0x80808080); /* .5 required in alpha for GL_DOT3_RGBA_EXT */
|
||||
|
||||
OUT_BATCH(_3DSTATE_MAP_COORD_SETBIND_CMD);
|
||||
OUT_BATCH(TEXBIND_SET3(TEXCOORDSRC_VTXSET_3) |
|
||||
TEXBIND_SET2(TEXCOORDSRC_VTXSET_2) |
|
||||
TEXBIND_SET1(TEXCOORDSRC_VTXSET_1) |
|
||||
TEXBIND_SET0(TEXCOORDSRC_VTXSET_0));
|
||||
|
||||
/* copy from mesa */
|
||||
OUT_BATCH(_3DSTATE_FOG_COLOR_CMD |
|
||||
FOG_COLOR_RED(0) | FOG_COLOR_GREEN(0) | FOG_COLOR_BLUE(0));
|
||||
|
||||
OUT_BATCH(_3DSTATE_CONST_BLEND_COLOR_CMD);
|
||||
OUT_BATCH(0);
|
||||
|
||||
OUT_BATCH(_3DSTATE_MODES_1_CMD |
|
||||
ENABLE_COLR_BLND_FUNC |
|
||||
BLENDFUNC_ADD |
|
||||
ENABLE_SRC_BLND_FACTOR |
|
||||
SRC_BLND_FACT(BLENDFACTOR_ONE) |
|
||||
ENABLE_DST_BLND_FACTOR | DST_BLND_FACT(BLENDFACTOR_ZERO));
|
||||
OUT_BATCH(_3DSTATE_MODES_2_CMD | ENABLE_GLOBAL_DEPTH_BIAS | GLOBAL_DEPTH_BIAS(0) | ENABLE_ALPHA_TEST_FUNC | ALPHA_TEST_FUNC(0) | /* always */
|
||||
ALPHA_REF_VALUE(0));
|
||||
OUT_BATCH(_3DSTATE_MODES_3_CMD |
|
||||
ENABLE_DEPTH_TEST_FUNC |
|
||||
DEPTH_TEST_FUNC(0x2) | /* COMPAREFUNC_LESS */
|
||||
ENABLE_ALPHA_SHADE_MODE |
|
||||
ALPHA_SHADE_MODE(SHADE_MODE_LINEAR) |
|
||||
ENABLE_FOG_SHADE_MODE |
|
||||
FOG_SHADE_MODE(SHADE_MODE_LINEAR) |
|
||||
ENABLE_SPEC_SHADE_MODE |
|
||||
SPEC_SHADE_MODE(SHADE_MODE_LINEAR) |
|
||||
ENABLE_COLOR_SHADE_MODE |
|
||||
COLOR_SHADE_MODE(SHADE_MODE_LINEAR) |
|
||||
ENABLE_CULL_MODE | CULLMODE_NONE);
|
||||
|
||||
OUT_BATCH(_3DSTATE_MODES_4_CMD |
|
||||
ENABLE_LOGIC_OP_FUNC |
|
||||
LOGIC_OP_FUNC(LOGICOP_COPY) |
|
||||
ENABLE_STENCIL_TEST_MASK |
|
||||
STENCIL_TEST_MASK(0xff) |
|
||||
ENABLE_STENCIL_WRITE_MASK | STENCIL_WRITE_MASK(0xff));
|
||||
|
||||
OUT_BATCH(_3DSTATE_STENCIL_TEST_CMD |
|
||||
ENABLE_STENCIL_PARMS |
|
||||
STENCIL_FAIL_OP(0) | /* STENCILOP_KEEP */
|
||||
STENCIL_PASS_DEPTH_FAIL_OP(0) | /* STENCILOP_KEEP */
|
||||
STENCIL_PASS_DEPTH_PASS_OP(0) | /* STENCILOP_KEEP */
|
||||
ENABLE_STENCIL_TEST_FUNC |
|
||||
STENCIL_TEST_FUNC(0) | /* COMPAREFUNC_ALWAYS */
|
||||
ENABLE_STENCIL_REF_VALUE |
|
||||
STENCIL_REF_VALUE(0));
|
||||
|
||||
OUT_BATCH(_3DSTATE_MODES_5_CMD |
|
||||
FLUSH_TEXTURE_CACHE |
|
||||
ENABLE_SPRITE_POINT_TEX | SPRITE_POINT_TEX_OFF |
|
||||
ENABLE_FIXED_LINE_WIDTH | FIXED_LINE_WIDTH(0x2) | /* 1.0 */
|
||||
ENABLE_FIXED_POINT_WIDTH | FIXED_POINT_WIDTH(1));
|
||||
|
||||
OUT_BATCH(_3DSTATE_STIPPLE);
|
||||
|
||||
/* Set default blend state */
|
||||
OUT_BATCH(_3DSTATE_MAP_BLEND_OP_CMD(0) |
|
||||
TEXPIPE_COLOR |
|
||||
ENABLE_TEXOUTPUT_WRT_SEL |
|
||||
TEXOP_OUTPUT_CURRENT |
|
||||
DISABLE_TEX_CNTRL_STAGE |
|
||||
TEXOP_SCALE_1X |
|
||||
TEXOP_MODIFY_PARMS | TEXOP_LAST_STAGE | TEXBLENDOP_ARG1);
|
||||
OUT_BATCH(_3DSTATE_MAP_BLEND_OP_CMD(0) |
|
||||
TEXPIPE_ALPHA |
|
||||
ENABLE_TEXOUTPUT_WRT_SEL |
|
||||
TEXOP_OUTPUT_CURRENT |
|
||||
TEXOP_SCALE_1X | TEXOP_MODIFY_PARMS | TEXBLENDOP_ARG1);
|
||||
OUT_BATCH(_3DSTATE_MAP_BLEND_ARG_CMD(0) |
|
||||
TEXPIPE_COLOR |
|
||||
TEXBLEND_ARG1 |
|
||||
TEXBLENDARG_MODIFY_PARMS | TEXBLENDARG_DIFFUSE);
|
||||
OUT_BATCH(_3DSTATE_MAP_BLEND_ARG_CMD(0) |
|
||||
TEXPIPE_ALPHA |
|
||||
TEXBLEND_ARG1 |
|
||||
TEXBLENDARG_MODIFY_PARMS | TEXBLENDARG_DIFFUSE);
|
||||
|
||||
OUT_BATCH(_3DSTATE_AA_CMD |
|
||||
AA_LINE_ECAAR_WIDTH_ENABLE |
|
||||
AA_LINE_ECAAR_WIDTH_1_0 |
|
||||
AA_LINE_REGION_WIDTH_ENABLE |
|
||||
AA_LINE_REGION_WIDTH_1_0 | AA_LINE_DISABLE);
|
||||
}
|
||||
|
||||
/* render target state */
|
||||
{
|
||||
uint32_t tiling_bits = 0;
|
||||
if (dst->tiling != I915_TILING_NONE)
|
||||
tiling_bits = BUF_3D_TILED_SURFACE;
|
||||
if (dst->tiling == I915_TILING_Y)
|
||||
tiling_bits |= BUF_3D_TILE_WALK_Y;
|
||||
|
||||
OUT_BATCH(_3DSTATE_BUF_INFO_CMD);
|
||||
OUT_BATCH(BUF_3D_ID_COLOR_BACK | tiling_bits |
|
||||
BUF_3D_PITCH(dst->stride));
|
||||
OUT_RELOC(dst->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
|
||||
|
||||
OUT_BATCH(_3DSTATE_DST_BUF_VARS_CMD);
|
||||
OUT_BATCH(COLR_BUF_ARGB8888 |
|
||||
DSTORG_HORT_BIAS(0x8) |
|
||||
DSTORG_VERT_BIAS(0x8));
|
||||
|
||||
OUT_BATCH(_3DSTATE_DRAW_RECT_CMD);
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(0); /* ymin, xmin */
|
||||
OUT_BATCH(DRAW_YMAX(buf_height(dst) - 1) |
|
||||
DRAW_XMAX(buf_width(dst) - 1));
|
||||
OUT_BATCH(0); /* yorig, xorig */
|
||||
}
|
||||
|
||||
/* dynamic state */
|
||||
{
|
||||
OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 |
|
||||
I1_LOAD_S(2) | I1_LOAD_S(3) | I1_LOAD_S(8) | 2);
|
||||
OUT_BATCH(1); /* number of coordinate sets */
|
||||
OUT_BATCH(S3_CULLMODE_NONE | S3_VERTEXHAS_XY);
|
||||
OUT_BATCH(S8_ENABLE_COLOR_BLEND | S8_BLENDFUNC_ADD |
|
||||
BLENDFACTOR_ONE << S8_SRC_BLEND_FACTOR_SHIFT |
|
||||
BLENDFACTOR_ZERO << S8_DST_BLEND_FACTOR_SHIFT |
|
||||
S8_ENABLE_COLOR_BUFFER_WRITE);
|
||||
|
||||
OUT_BATCH(_3DSTATE_INDPT_ALPHA_BLEND_CMD | DISABLE_INDPT_ALPHA_BLEND);
|
||||
|
||||
OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_2 |
|
||||
LOAD_TEXTURE_BLEND_STAGE(0) | 1);
|
||||
OUT_BATCH(TB0C_LAST_STAGE | TB0C_RESULT_SCALE_1X | TB0C_OP_MODULE |
|
||||
TB0C_OUTPUT_WRITE_CURRENT | TB0C_ARG1_SEL_TEXEL0 |
|
||||
TB0C_ARG2_SEL_ONE);
|
||||
OUT_BATCH(TB0A_RESULT_SCALE_1X | TB0A_OP_MODULE |
|
||||
TB0A_OUTPUT_WRITE_CURRENT | TB0A_ARG1_SEL_TEXEL0 |
|
||||
TB0A_ARG2_SEL_ONE);
|
||||
|
||||
OUT_BATCH(_3DSTATE_ENABLES_1_CMD | DISABLE_LOGIC_OP |
|
||||
DISABLE_STENCIL_TEST | DISABLE_DEPTH_BIAS |
|
||||
DISABLE_SPEC_ADD | DISABLE_FOG | DISABLE_ALPHA_TEST |
|
||||
ENABLE_COLOR_BLEND | DISABLE_DEPTH_TEST);
|
||||
/* We have to explicitly say we don't want write disabled */
|
||||
OUT_BATCH(_3DSTATE_ENABLES_2_CMD | ENABLE_COLOR_MASK |
|
||||
DISABLE_STENCIL_WRITE | ENABLE_TEX_CACHE |
|
||||
DISABLE_DITHER | ENABLE_COLOR_WRITE | DISABLE_DEPTH_WRITE);
|
||||
|
||||
OUT_BATCH(_3DSTATE_VERTEX_FORMAT_2_CMD |
|
||||
TEXCOORDFMT_2D << 0);
|
||||
}
|
||||
|
||||
/* sampler state */
|
||||
{
|
||||
uint32_t tiling_bits = 0;
|
||||
if (src->tiling != I915_TILING_NONE)
|
||||
tiling_bits = TM0S1_TILED_SURFACE;
|
||||
if (src->tiling == I915_TILING_Y)
|
||||
tiling_bits |= TM0S1_TILE_WALK;
|
||||
|
||||
OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_2 |
|
||||
LOAD_TEXTURE_MAP(0) | 4);
|
||||
OUT_RELOC(src->bo, I915_GEM_DOMAIN_SAMPLER, 0, 0);
|
||||
OUT_BATCH((buf_height(src) - 1) << TM0S1_HEIGHT_SHIFT |
|
||||
(buf_width(src) - 1) << TM0S1_WIDTH_SHIFT |
|
||||
MAPSURF_32BIT | MT_32BIT_ARGB8888 | tiling_bits);
|
||||
OUT_BATCH((src->stride / 4 - 1) << TM0S2_PITCH_SHIFT | TM0S2_MAP_2D);
|
||||
OUT_BATCH(FILTER_NEAREST << TM0S3_MAG_FILTER_SHIFT |
|
||||
FILTER_NEAREST << TM0S3_MIN_FILTER_SHIFT |
|
||||
MIPFILTER_NONE << TM0S3_MIP_FILTER_SHIFT);
|
||||
OUT_BATCH(0); /* default color */
|
||||
OUT_BATCH(_3DSTATE_MAP_COORD_SET_CMD | TEXCOORD_SET(0) |
|
||||
ENABLE_TEXCOORD_PARAMS | TEXCOORDS_ARE_NORMAL |
|
||||
TEXCOORDTYPE_CARTESIAN |
|
||||
ENABLE_ADDR_V_CNTL | TEXCOORD_ADDR_V_MODE(TEXCOORDMODE_CLAMP_BORDER) |
|
||||
ENABLE_ADDR_U_CNTL | TEXCOORD_ADDR_U_MODE(TEXCOORDMODE_CLAMP_BORDER));
|
||||
/* map texel stream */
|
||||
OUT_BATCH(_3DSTATE_MAP_COORD_SETBIND_CMD);
|
||||
OUT_BATCH(TEXBIND_SET0(TEXCOORDSRC_VTXSET_0) |
|
||||
TEXBIND_SET1(TEXCOORDSRC_KEEP) |
|
||||
TEXBIND_SET2(TEXCOORDSRC_KEEP) |
|
||||
TEXBIND_SET3(TEXCOORDSRC_KEEP));
|
||||
OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD | (0 << 16) |
|
||||
DISABLE_TEX_STREAM_BUMP |
|
||||
ENABLE_TEX_STREAM_COORD_SET |
|
||||
TEX_STREAM_COORD_SET(0) |
|
||||
ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(0));
|
||||
}
|
||||
|
||||
OUT_BATCH(PRIM3D_INLINE | PRIM3D_RECTLIST | (3*4 -1));
|
||||
emit_vertex(batch, dst_x + width);
|
||||
emit_vertex(batch, dst_y + height);
|
||||
emit_vertex_normalized(batch, src_x + width, buf_width(src));
|
||||
emit_vertex_normalized(batch, src_y + height, buf_height(src));
|
||||
|
||||
emit_vertex(batch, dst_x);
|
||||
emit_vertex(batch, dst_y + height);
|
||||
emit_vertex_normalized(batch, src_x, buf_width(src));
|
||||
emit_vertex_normalized(batch, src_y + height, buf_height(src));
|
||||
|
||||
emit_vertex(batch, dst_x);
|
||||
emit_vertex(batch, dst_y);
|
||||
emit_vertex_normalized(batch, src_x, buf_width(src));
|
||||
emit_vertex_normalized(batch, src_y, buf_height(src));
|
||||
|
||||
intel_batchbuffer_flush(batch);
|
||||
}
|
||||
@@ -0,0 +1,180 @@
|
||||
#include "i915_reg.h"
|
||||
#include "i915_3d.h"
|
||||
#include "rendercopy.h"
|
||||
|
||||
void gen3_render_copyfunc(struct intel_batchbuffer *batch,
|
||||
struct scratch_buf *src, unsigned src_x, unsigned src_y,
|
||||
unsigned width, unsigned height,
|
||||
struct scratch_buf *dst, unsigned dst_x, unsigned dst_y)
|
||||
{
|
||||
/* invariant state */
|
||||
{
|
||||
OUT_BATCH(_3DSTATE_AA_CMD |
|
||||
AA_LINE_ECAAR_WIDTH_ENABLE |
|
||||
AA_LINE_ECAAR_WIDTH_1_0 |
|
||||
AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);
|
||||
OUT_BATCH(_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD |
|
||||
IAB_MODIFY_ENABLE |
|
||||
IAB_MODIFY_FUNC | (BLENDFUNC_ADD << IAB_FUNC_SHIFT) |
|
||||
IAB_MODIFY_SRC_FACTOR | (BLENDFACT_ONE <<
|
||||
IAB_SRC_FACTOR_SHIFT) |
|
||||
IAB_MODIFY_DST_FACTOR | (BLENDFACT_ZERO <<
|
||||
IAB_DST_FACTOR_SHIFT));
|
||||
OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS |
|
||||
CSB_TCB(0, 0) |
|
||||
CSB_TCB(1, 1) |
|
||||
CSB_TCB(2, 2) |
|
||||
CSB_TCB(3, 3) |
|
||||
CSB_TCB(4, 4) |
|
||||
CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7));
|
||||
OUT_BATCH(_3DSTATE_RASTER_RULES_CMD |
|
||||
ENABLE_POINT_RASTER_RULE |
|
||||
OGL_POINT_RASTER_RULE |
|
||||
ENABLE_LINE_STRIP_PROVOKE_VRTX |
|
||||
ENABLE_TRI_FAN_PROVOKE_VRTX |
|
||||
LINE_STRIP_PROVOKE_VRTX(1) |
|
||||
TRI_FAN_PROVOKE_VRTX(2) | ENABLE_TEXKILL_3D_4D | TEXKILL_4D);
|
||||
OUT_BATCH(_3DSTATE_MODES_4_CMD |
|
||||
ENABLE_LOGIC_OP_FUNC | LOGIC_OP_FUNC(LOGICOP_COPY) |
|
||||
ENABLE_STENCIL_WRITE_MASK | STENCIL_WRITE_MASK(0xff) |
|
||||
ENABLE_STENCIL_TEST_MASK | STENCIL_TEST_MASK(0xff));
|
||||
OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | I1_LOAD_S(4) | I1_LOAD_S(5) | 2);
|
||||
OUT_BATCH(0x00000000); /* Disable texture coordinate wrap-shortest */
|
||||
OUT_BATCH((1 << S4_POINT_WIDTH_SHIFT) |
|
||||
S4_LINE_WIDTH_ONE |
|
||||
S4_CULLMODE_NONE |
|
||||
S4_VFMT_XY);
|
||||
OUT_BATCH(0x00000000); /* Stencil. */
|
||||
OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
|
||||
OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD);
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(_3DSTATE_DEPTH_SUBRECT_DISABLE);
|
||||
OUT_BATCH(_3DSTATE_LOAD_INDIRECT | 0); /* disable indirect state */
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(_3DSTATE_STIPPLE);
|
||||
OUT_BATCH(0x00000000);
|
||||
OUT_BATCH(_3DSTATE_BACKFACE_STENCIL_OPS | BFO_ENABLE_STENCIL_TWO_SIDE | 0);
|
||||
}
|
||||
|
||||
/* samler state */
|
||||
{
|
||||
#define TEX_COUNT 1
|
||||
uint32_t tiling_bits = 0;
|
||||
if (src->tiling != I915_TILING_NONE)
|
||||
tiling_bits = MS3_TILED_SURFACE;
|
||||
if (src->tiling == I915_TILING_Y)
|
||||
tiling_bits |= MS3_TILE_WALK;
|
||||
|
||||
OUT_BATCH(_3DSTATE_MAP_STATE | (3 * TEX_COUNT));
|
||||
OUT_BATCH((1 << TEX_COUNT) - 1);
|
||||
OUT_RELOC(src->bo, I915_GEM_DOMAIN_SAMPLER, 0, 0);
|
||||
OUT_BATCH(MAPSURF_32BIT | MT_32BIT_ARGB8888 |
|
||||
tiling_bits |
|
||||
(buf_height(src) - 1) << MS3_HEIGHT_SHIFT |
|
||||
(buf_width(src) - 1) << MS3_WIDTH_SHIFT);
|
||||
OUT_BATCH((src->stride/4-1) << MS4_PITCH_SHIFT);
|
||||
|
||||
OUT_BATCH(_3DSTATE_SAMPLER_STATE | (3 * TEX_COUNT));
|
||||
OUT_BATCH((1 << TEX_COUNT) - 1);
|
||||
OUT_BATCH(MIPFILTER_NONE << SS2_MIP_FILTER_SHIFT |
|
||||
FILTER_NEAREST << SS2_MAG_FILTER_SHIFT |
|
||||
FILTER_NEAREST << SS2_MIN_FILTER_SHIFT);
|
||||
OUT_BATCH(TEXCOORDMODE_WRAP << SS3_TCX_ADDR_MODE_SHIFT |
|
||||
TEXCOORDMODE_WRAP << SS3_TCY_ADDR_MODE_SHIFT |
|
||||
0 << SS3_TEXTUREMAP_INDEX_SHIFT);
|
||||
OUT_BATCH(0x00000000);
|
||||
}
|
||||
|
||||
/* render target state */
|
||||
{
|
||||
uint32_t tiling_bits = 0;
|
||||
if (dst->tiling != I915_TILING_NONE)
|
||||
tiling_bits = BUF_3D_TILED_SURFACE;
|
||||
if (dst->tiling == I915_TILING_Y)
|
||||
tiling_bits |= BUF_3D_TILE_WALK_Y;
|
||||
|
||||
OUT_BATCH(_3DSTATE_BUF_INFO_CMD);
|
||||
OUT_BATCH(BUF_3D_ID_COLOR_BACK | tiling_bits |
|
||||
BUF_3D_PITCH(dst->stride));
|
||||
OUT_RELOC(dst->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
|
||||
|
||||
OUT_BATCH(_3DSTATE_DST_BUF_VARS_CMD);
|
||||
OUT_BATCH(COLR_BUF_ARGB8888 |
|
||||
DSTORG_HORT_BIAS(0x8) |
|
||||
DSTORG_VERT_BIAS(0x8));
|
||||
|
||||
/* draw rect is unconditional */
|
||||
OUT_BATCH(_3DSTATE_DRAW_RECT_CMD);
|
||||
OUT_BATCH(0x00000000);
|
||||
OUT_BATCH(0x00000000); /* ymin, xmin */
|
||||
OUT_BATCH(DRAW_YMAX(buf_height(dst) - 1) |
|
||||
DRAW_XMAX(buf_width(dst) - 1));
|
||||
/* yorig, xorig (relate to color buffer?) */
|
||||
OUT_BATCH(0x00000000);
|
||||
}
|
||||
|
||||
/* texfmt */
|
||||
{
|
||||
OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 |
|
||||
I1_LOAD_S(1) | I1_LOAD_S(2) | I1_LOAD_S(6) | 2);
|
||||
OUT_BATCH((4 << S1_VERTEX_WIDTH_SHIFT) |
|
||||
(4 << S1_VERTEX_PITCH_SHIFT));
|
||||
OUT_BATCH(~S2_TEXCOORD_FMT(0, TEXCOORDFMT_NOT_PRESENT) | S2_TEXCOORD_FMT(0, TEXCOORDFMT_2D));
|
||||
OUT_BATCH(S6_CBUF_BLEND_ENABLE | S6_COLOR_WRITE_ENABLE |
|
||||
BLENDFUNC_ADD << S6_CBUF_BLEND_FUNC_SHIFT |
|
||||
BLENDFACT_ONE << S6_CBUF_SRC_BLEND_FACT_SHIFT |
|
||||
BLENDFACT_ZERO << S6_CBUF_DST_BLEND_FACT_SHIFT);
|
||||
}
|
||||
|
||||
/* frage shader */
|
||||
{
|
||||
OUT_BATCH(_3DSTATE_PIXEL_SHADER_PROGRAM | (1 + 3*3 - 2));
|
||||
/* decl FS_T0 */
|
||||
OUT_BATCH(D0_DCL |
|
||||
REG_TYPE(FS_T0) << D0_TYPE_SHIFT |
|
||||
REG_NR(FS_T0) << D0_NR_SHIFT |
|
||||
((REG_TYPE(FS_T0) != REG_TYPE_S) ? D0_CHANNEL_ALL : 0));
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(0);
|
||||
/* decl FS_S0 */
|
||||
OUT_BATCH(D0_DCL |
|
||||
(REG_TYPE(FS_S0) << D0_TYPE_SHIFT) |
|
||||
(REG_NR(FS_S0) << D0_NR_SHIFT) |
|
||||
((REG_TYPE(FS_S0) != REG_TYPE_S) ? D0_CHANNEL_ALL : 0));
|
||||
OUT_BATCH(0);
|
||||
OUT_BATCH(0);
|
||||
/* texld(FS_OC, FS_S0, FS_T0 */
|
||||
OUT_BATCH(T0_TEXLD |
|
||||
(REG_TYPE(FS_OC) << T0_DEST_TYPE_SHIFT) |
|
||||
(REG_NR(FS_OC) << T0_DEST_NR_SHIFT) |
|
||||
(REG_NR(FS_S0) << T0_SAMPLER_NR_SHIFT));
|
||||
OUT_BATCH((REG_TYPE(FS_T0) << T1_ADDRESS_REG_TYPE_SHIFT) |
|
||||
(REG_NR(FS_T0) << T1_ADDRESS_REG_NR_SHIFT));
|
||||
OUT_BATCH(0);
|
||||
}
|
||||
|
||||
OUT_BATCH(PRIM3D_RECTLIST | (3*4 - 1));
|
||||
emit_vertex(batch, dst_x + width);
|
||||
emit_vertex(batch, dst_y + height);
|
||||
emit_vertex(batch, src_x + width);
|
||||
emit_vertex(batch, src_y + height);
|
||||
|
||||
emit_vertex(batch, dst_x);
|
||||
emit_vertex(batch, dst_y + height);
|
||||
emit_vertex(batch, src_x);
|
||||
emit_vertex(batch, src_y + height);
|
||||
|
||||
emit_vertex(batch, dst_x);
|
||||
emit_vertex(batch, dst_y);
|
||||
emit_vertex(batch, src_x);
|
||||
emit_vertex(batch, src_y);
|
||||
|
||||
intel_batchbuffer_flush(batch);
|
||||
}
|
||||
+1553
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,72 @@
|
||||
#include <stdlib.h>
|
||||
#include <sys/ioctl.h>
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include <assert.h>
|
||||
#include <fcntl.h>
|
||||
#include <inttypes.h>
|
||||
#include <errno.h>
|
||||
#include <sys/stat.h>
|
||||
#include <sys/time.h>
|
||||
#include <getopt.h>
|
||||
#include "drm.h"
|
||||
#include "i915_drm.h"
|
||||
#include "drmtest.h"
|
||||
#include "intel_bufmgr.h"
|
||||
#include "intel_batchbuffer.h"
|
||||
#include "intel_gpu_tools.h"
|
||||
|
||||
struct scratch_buf {
|
||||
drm_intel_bo *bo;
|
||||
uint32_t stride;
|
||||
uint32_t tiling;
|
||||
uint32_t *data;
|
||||
uint32_t *cpu_mapping;
|
||||
uint32_t size;
|
||||
unsigned num_tiles;
|
||||
};
|
||||
|
||||
static inline void emit_vertex_2s(struct intel_batchbuffer *batch,
|
||||
int16_t x, int16_t y)
|
||||
{
|
||||
OUT_BATCH((uint16_t)y << 16 | (uint16_t)x);
|
||||
}
|
||||
|
||||
static inline void emit_vertex(struct intel_batchbuffer *batch,
|
||||
float f)
|
||||
{
|
||||
union { float f; uint32_t ui; } u;
|
||||
u.f = f;
|
||||
OUT_BATCH(u.ui);
|
||||
}
|
||||
|
||||
static inline void emit_vertex_normalized(struct intel_batchbuffer *batch,
|
||||
float f, float total)
|
||||
{
|
||||
union { float f; uint32_t ui; } u;
|
||||
u.f = f / total;
|
||||
OUT_BATCH(u.ui);
|
||||
}
|
||||
|
||||
static inline unsigned buf_width(struct scratch_buf *buf)
|
||||
{
|
||||
return buf->stride/sizeof(uint32_t);
|
||||
}
|
||||
|
||||
static inline unsigned buf_height(struct scratch_buf *buf)
|
||||
{
|
||||
return buf->size/buf->stride;
|
||||
}
|
||||
|
||||
void gen6_render_copyfunc(struct intel_batchbuffer *batch,
|
||||
struct scratch_buf *src, unsigned src_x, unsigned src_y,
|
||||
unsigned width, unsigned height,
|
||||
struct scratch_buf *dst, unsigned dst_x, unsigned dst_y);
|
||||
void gen3_render_copyfunc(struct intel_batchbuffer *batch,
|
||||
struct scratch_buf *src, unsigned src_x, unsigned src_y,
|
||||
unsigned width, unsigned height,
|
||||
struct scratch_buf *dst, unsigned dst_x, unsigned dst_y);
|
||||
void gen2_render_copyfunc(struct intel_batchbuffer *batch,
|
||||
struct scratch_buf *src, unsigned src_x, unsigned src_y,
|
||||
unsigned width, unsigned height,
|
||||
struct scratch_buf *dst, unsigned dst_x, unsigned dst_y);
|
||||
Reference in New Issue
Block a user