flywithu/ntel-gpu-tools
1
0
Fork 0
mirror of https://github.com/tiagovignatti/intel-gpu-tools.git synced 2025-06-12 10:26:12 +00:00
Code Issues Releases Wiki Activity

Comment cleanup and add missing semicolons after rules.

Browse Source
This commit is contained in:
Eric Anholt 2006-08-25 17:42:05 -07:00 committed by Damien Lespiau
parent 908f37d92d
commit edc82a045c
1 changed files with 18 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
assembler/gram.y
View File

@ -190,6 +190,7 @@ binaryinstruction:
; ;
binaryop: MUL | MAC | MACH | LINE | SAD2 | SADA2 | DP4 | DPH | DP3 | DP2 binaryop: MUL | MAC | MACH | LINE | SAD2 | SADA2 | DP4 | DPH | DP3 | DP2
;
binaryaccinstruction: binaryaccinstruction:
predicate binaryaccop conditionalmodifier saturate execsize predicate binaryaccop conditionalmodifier saturate execsize
@ -211,6 +212,7 @@ binaryaccop: AVG | ADD | SEL | AND | OR | XOR | SHR | SHL | ASR | CMP | CMPN
; ;
triinstruction: sendinstruction triinstruction: sendinstruction
;
sendinstruction: predicate SEND execsize INTEGER post_dst payload msgtarget sendinstruction: predicate SEND execsize INTEGER post_dst payload msgtarget
MSGLEN INTEGER RETURNLEN INTEGER instoptions MSGLEN INTEGER RETURNLEN INTEGER instoptions
@ -238,11 +240,13 @@ sendinstruction: predicate SEND execsize INTEGER post_dst payload msgtarget
$$.bits3.generic.end_of_thread = $$.bits3.generic.end_of_thread =
$12.bits3.generic.end_of_thread; $12.bits3.generic.end_of_thread;
} }
;
branchloopop: IF | IFF | WHILE branchloopop: IF | IFF | WHILE
; ;
breakop: BREAK | CONT | WAIT breakop: BREAK | CONT | WAIT
;
maskpushop: MSAVE | PUSH maskpushop: MSAVE | PUSH
; ;
@ -252,6 +256,7 @@ specialinstruction: NOP
bzero(&$$, sizeof($$)); bzero(&$$, sizeof($$));
$$.header.opcode = $1; $$.header.opcode = $1;
} }
;
/* XXX! */ /* XXX! */
payload: directsrcoperand payload: directsrcoperand
@ -368,16 +373,18 @@ math_function: INV | LOG | EXP | SQRT | POW | SIN | COS | SINCOS | INTDIV
math_signed: /* empty */ { $$ = 0; } math_signed: /* empty */ { $$ = 0; }
| SIGNED { $$ = 1; } | SIGNED { $$ = 1; }
;
math_scalar: /* empty */ { $$ = 0; } math_scalar: /* empty */ { $$ = 0; }
| SCALAR { $$ = 1; } | SCALAR { $$ = 1; }
;
/* 1.4.2: Destination register */ /* 1.4.2: Destination register */
dst: dstoperand | dstoperandex dst: dstoperand | dstoperandex
; ;
/* XXX: dstregion writemask */ /* XXX: writemask */
dstoperand: dstreg dstregion regtype dstoperand: dstreg dstregion regtype
{ {
/* Returns an instruction with just the destination register /* Returns an instruction with just the destination register
@ -437,7 +444,7 @@ dstoperandex: dstoperandex_typed dstregion regtype
dstoperandex_typed: accreg | flagreg | addrreg | maskreg dstoperandex_typed: accreg | flagreg | addrreg | maskreg
; ;
/* XXX: indirectgenreg, directmsgreg, indirectmsgreg */ /* XXX: indirectgenreg, indirectmsgreg */
dstreg: directgenreg dstreg: directgenreg
{ {
$$.bits1.da1.dest_reg_file = $1.reg_file; $$.bits1.da1.dest_reg_file = $1.reg_file;
@ -461,6 +468,7 @@ srcacc: directsrcaccoperand
; ;
srcimm: directsrcoperand | imm32reg srcimm: directsrcoperand | imm32reg
;
imm32reg: imm32 srcimmtype imm32reg: imm32 srcimmtype
{ {
@ -568,6 +576,7 @@ directsrcoperand:
| srcarchoperandex | srcarchoperandex
; ;
/* 1.4.5: Register files and register numbers */
subregnum: DOT INTEGER subregnum: DOT INTEGER
{ {
$$ = $2; $$ = $2;
@ -579,13 +588,13 @@ subregnum: DOT INTEGER
} }
; ;
/* 1.4.5: Register files and register numbers */
directgenreg: GENREG subregnum directgenreg: GENREG subregnum
{ {
$$.reg_file = BRW_GENERAL_REGISTER_FILE; $$.reg_file = BRW_GENERAL_REGISTER_FILE;
$$.reg_nr = $1; $$.reg_nr = $1;
$$.subreg_nr = $2; $$.subreg_nr = $2;
} }
;
directmsgreg: MSGREG subregnum directmsgreg: MSGREG subregnum
{ {
@ -794,13 +803,16 @@ regtype: TYPE_F { $$ = BRW_REGISTER_TYPE_F; }
| TYPE_W { $$ = BRW_REGISTER_TYPE_W; } | TYPE_W { $$ = BRW_REGISTER_TYPE_W; }
| TYPE_UB { $$ = BRW_REGISTER_TYPE_UB; } | TYPE_UB { $$ = BRW_REGISTER_TYPE_UB; }
| TYPE_B { $$ = BRW_REGISTER_TYPE_B; } | TYPE_B { $$ = BRW_REGISTER_TYPE_B; }
;
/* XXX: Add TYPE_VF and TYPE_HF */ /* XXX: Add TYPE_VF and TYPE_HF */
srcimmtype: regtype srcimmtype: regtype
; ;
/* 1.4.11: */ /* 1.4.11: Immediate values */
imm32: INTEGER { $$ = $1; } imm32: INTEGER { $$ = $1; }
| NUMBER { $$ = $1; } | NUMBER { $$ = $1; }
;
/* 1.4.12: Predication and modifiers */ /* 1.4.12: Predication and modifiers */
/* XXX: do the predicate */ /* XXX: do the predicate */
@ -809,9 +821,11 @@ predicate:
negate: /* empty */ { $$ = 0; } negate: /* empty */ { $$ = 0; }
| MINUS { $$ = 1; } | MINUS { $$ = 1; }
;
abs: /* empty */ { $$ = 0; } abs: /* empty */ { $$ = 0; }
| ABS { $$ = 1; } | ABS { $$ = 1; }
;
execsize: LPAREN INTEGER RPAREN execsize: LPAREN INTEGER RPAREN
{ {