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https://github.com/tiagovignatti/intel-gpu-tools.git
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tests/kms_mmio_vs_cs_flip: Add a test case to exercise mmio vs. CS flip races
kms_mmio_vs_cs_flip has two subtests:
- setplane_vs_cs_flip tests the interaction between
fullscreen sprites and CS flips
- setcrtc_vs_cs_flip tests the interaction between
primary plane panning and CS flips
v2: Skip sprite test when there are no sprites
Reduce busy_bo to 64MB (now works on my gen2)
Handle pipe vs. port incompatibility
v3: Handle missing auto pipe crc
Reviewed-by Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
This commit is contained in:
Ville Syrjälä
parent
e2ac7a15f1
commit
eb566561e7
@ -64,6 +64,7 @@ TESTS_progs_M = \
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kms_fence_pin_leak \
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kms_flip \
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kms_flip_tiling \
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kms_mmio_vs_cs_flip \
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kms_pipe_crc_basic \
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kms_plane \
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kms_render \
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580
tests/kms_mmio_vs_cs_flip.c
Normal file
580
tests/kms_mmio_vs_cs_flip.c
Normal file
@ -0,0 +1,580 @@
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/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include <errno.h>
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#include <stdbool.h>
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#include <stdio.h>
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#include <string.h>
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#include <time.h>
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#include "drmtest.h"
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#include "igt_debugfs.h"
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#include "igt_kms.h"
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#include "intel_chipset.h"
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#include "ioctl_wrappers.h"
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typedef struct {
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int drm_fd;
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igt_display_t display;
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igt_pipe_crc_t *pipe_crc;
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drm_intel_bufmgr *bufmgr;
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drm_intel_bo *busy_bo;
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uint32_t devid;
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bool flip_done;
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} data_t;
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static void exec_nop(data_t *data, uint32_t handle, unsigned int ring)
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{
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struct intel_batchbuffer *batch;
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drm_intel_bo *bo;
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batch = intel_batchbuffer_alloc(data->bufmgr, data->devid);
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igt_assert(batch);
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bo = gem_handle_to_libdrm_bo(data->bufmgr, data->drm_fd, "", handle);
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igt_assert(bo);
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/* add relocs to make sure the kernel will think we write to dst */
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BEGIN_BATCH(4);
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OUT_BATCH(MI_BATCH_BUFFER_END);
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OUT_BATCH(MI_NOOP);
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OUT_RELOC(bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
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OUT_BATCH(MI_NOOP);
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ADVANCE_BATCH();
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intel_batchbuffer_flush_on_ring(batch, ring);
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intel_batchbuffer_free(batch);
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drm_intel_bo_unreference(bo);
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}
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static void exec_blt(data_t *data)
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{
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struct intel_batchbuffer *batch;
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int w, h, pitch, i;
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batch = intel_batchbuffer_alloc(data->bufmgr, data->devid);
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igt_assert(batch);
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w = 8192;
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h = data->busy_bo->size / (8192 * 4);
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pitch = w * 4;
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for (i = 0; i < 40; i++) {
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BLIT_COPY_BATCH_START(data->devid, 0);
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OUT_BATCH((3 << 24) | /* 32 bits */
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(0xcc << 16) | /* copy ROP */
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pitch);
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OUT_BATCH(0 << 16 | 0);
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OUT_BATCH(h << 16 | w);
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OUT_RELOC(data->busy_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
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BLIT_RELOC_UDW(data->devid);
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OUT_BATCH(0 << 16 | 0);
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OUT_BATCH(pitch);
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OUT_RELOC(data->busy_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
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BLIT_RELOC_UDW(data->devid);
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ADVANCE_BATCH();
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}
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intel_batchbuffer_flush(batch);
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intel_batchbuffer_free(batch);
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}
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static void page_flip_handler(int fd, unsigned int frame, unsigned int sec,
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unsigned int usec, void *_data)
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{
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data_t *data = _data;
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data->flip_done = true;
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}
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static void wait_for_flip(data_t *data, uint32_t flip_handle)
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{
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struct timeval timeout = {
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.tv_sec = 3,
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.tv_usec = 0,
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};
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drmEventContext evctx = {
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.version = DRM_EVENT_CONTEXT_VERSION,
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.page_flip_handler = page_flip_handler,
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};
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fd_set fds;
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FD_ZERO(&fds);
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FD_SET(data->drm_fd, &fds);
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while (!data->flip_done) {
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int ret = select(data->drm_fd + 1, &fds, NULL, NULL, &timeout);
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if (ret < 0 && errno == EINTR)
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continue;
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igt_assert(ret >= 0);
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do_or_die(drmHandleEvent(data->drm_fd, &evctx));
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}
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/*
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* The flip completion may have been signalled prematurely, so
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* also submit another nop batch and wait for it to make sure
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* the ring has really been drained.
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*/
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if (IS_GEN7(data->devid) || IS_GEN8(data->devid))
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exec_nop(data, flip_handle, I915_EXEC_BLT);
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else
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exec_nop(data, flip_handle, I915_EXEC_RENDER);
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gem_sync(data->drm_fd, flip_handle);
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}
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static void make_gpu_busy(data_t *data, uint32_t flip_handle)
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{
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/*
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* Make sure flip_handle has been used on the blt ring.
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* This should make the flip use the same ring on gen7+.
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*/
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if (IS_GEN7(data->devid) || IS_GEN8(data->devid))
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exec_nop(data, flip_handle, I915_EXEC_BLT);
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/*
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* Add a pile commands to the ring. The flip will be
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* stuck behing these commands and hence gets delayed
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* significantly.
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*/
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exec_blt(data);
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/*
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* Make sure the render ring will block until the blt ring is clear.
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* This is in case the flip will execute on the render ring and the
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* blits were on the blt ring (this will be the case on gen6 at least).
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*
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* We can't add an explicit dependency between flip_handle and the
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* blits since that would cause the driver to block until the blits
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* have completed before it will perform a subsequent mmio flip,
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* and so the test would fail to exercise the mmio vs. CS flip race.
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*/
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if (HAS_BLT_RING(data->devid))
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exec_nop(data, data->busy_bo->handle, I915_EXEC_RENDER);
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}
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/*
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* 1. set primary plane to full red
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* 2. grab a reference crc
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* 3. set primary plane to full blue
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* 4. queue lots of GPU activity to delay the subsequent page flip
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* 5. queue a page flip to the same blue fb
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* 6. toggle a fullscreen sprite (green) on and back off again
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* 7. set primary plane to red fb
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* 8. wait for GPU to finish
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* 9. compare current crc with reference crc
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*
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* We expect the primary plane to display full red at the end.
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* If the sprite operations have interfered with the page flip,
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* the driver may have mistakenly completed the flip before
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* it was executed by the CS, and hence the subsequent mmio
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* flips may have overtaken it. So once we've finished everything
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* the CS flip may have been the last thing to occur, which means
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* the primary plane may be full blue instead of the red it's
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* supposed to be.
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*/
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static bool
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test_plane(data_t *data, igt_output_t *output, enum pipe pipe, enum igt_plane plane)
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{
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struct igt_fb red_fb, green_fb, blue_fb;
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drmModeModeInfo *mode;
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igt_plane_t *primary, *sprite;
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igt_crc_t ref_crc, crc;
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int ret;
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igt_output_set_pipe(output, pipe);
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igt_display_commit(&data->display);
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if (!output->valid) {
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igt_output_set_pipe(output, PIPE_ANY);
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igt_display_commit(&data->display);
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return false;
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}
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primary = igt_output_get_plane(output, 0);
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sprite = igt_output_get_plane(output, plane);
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mode = igt_output_get_mode(output);
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igt_create_color_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
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DRM_FORMAT_XRGB8888,
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false, /* tiled */
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1.0, 0.0, 0.0,
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&red_fb);
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igt_create_color_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
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DRM_FORMAT_XRGB8888,
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false, /* tiled */
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0.0, 1.0, 0.0,
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&green_fb);
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igt_create_color_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
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DRM_FORMAT_XRGB8888,
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false, /* tiled */
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0.0, 0.0, 1.0,
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&blue_fb);
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/*
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* Make sure these buffers are suited for display use
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* because most of the modeset operations must be fast
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* later on.
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*/
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igt_plane_set_fb(primary, &blue_fb);
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igt_display_commit(&data->display);
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igt_plane_set_fb(sprite, &green_fb);
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igt_display_commit(&data->display);
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igt_plane_set_fb(sprite, NULL);
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igt_display_commit(&data->display);
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if (data->pipe_crc)
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igt_pipe_crc_free(data->pipe_crc);
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data->pipe_crc = igt_pipe_crc_new(pipe, INTEL_PIPE_CRC_SOURCE_AUTO);
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if (!data->pipe_crc) {
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igt_info("auto crc not supported on this connector with crtc %i\n",
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pipe);
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igt_plane_set_fb(primary, NULL);
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igt_plane_set_fb(sprite, NULL);
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igt_output_set_pipe(output, PIPE_ANY);
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igt_display_commit(&data->display);
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igt_remove_fb(data->drm_fd, &red_fb);
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igt_remove_fb(data->drm_fd, &green_fb);
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igt_remove_fb(data->drm_fd, &blue_fb);
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return false;
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}
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/* set red fb and grab reference crc */
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igt_plane_set_fb(primary, &red_fb);
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igt_display_commit(&data->display);
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igt_pipe_crc_collect_crc(data->pipe_crc, &ref_crc);
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ret = drmModeSetCrtc(data->drm_fd, output->config.crtc->crtc_id,
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blue_fb.fb_id, 0, 0, &output->id, 1,
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mode);
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igt_assert(ret == 0);
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make_gpu_busy(data, blue_fb.gem_handle);
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data->flip_done = false;
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ret = drmModePageFlip(data->drm_fd, output->config.crtc->crtc_id,
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blue_fb.fb_id, DRM_MODE_PAGE_FLIP_EVENT, data);
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igt_assert(ret == 0);
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/*
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* Toggle a fullscreen sprite on and back off. This will result
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* in the primary plane getting disabled and re-enbled, and that
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* leads to mmio flips. The driver may then mistake the flip done
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* interrupts from the mmio flips as the flip done interrupts for
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* the CS flip, and hence subsequent mmio flips won't wait for the
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* CS flips like they should.
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*/
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ret = drmModeSetPlane(data->drm_fd,
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sprite->drm_plane->plane_id,
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output->config.crtc->crtc_id,
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green_fb.fb_id, 0,
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0, 0, mode->hdisplay, mode->vdisplay,
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0, 0, mode->hdisplay << 16, mode->vdisplay << 16);
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igt_assert(ret == 0);
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ret = drmModeSetPlane(data->drm_fd,
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sprite->drm_plane->plane_id,
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output->config.crtc->crtc_id,
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0, 0,
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0, 0, 0, 0,
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0, 0, 0, 0);
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igt_assert(ret == 0);
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/*
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* Set primary plane to red fb. This should wait for the CS flip
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* to complete. But if the kernel mistook the flip done interrupt
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* from the mmio flip as the flip done from the CS flip, this will
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* not wait for anything. And hence the the CS flip will actually
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* occur after this mmio flip.
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*/
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ret = drmModeSetCrtc(data->drm_fd, output->config.crtc->crtc_id,
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red_fb.fb_id, 0, 0, &output->id, 1,
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mode);
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igt_assert(ret == 0);
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/* Make sure the flip has been executed */
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wait_for_flip(data, blue_fb.gem_handle);
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/* Grab crc and compare with the extected result */
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igt_pipe_crc_collect_crc(data->pipe_crc, &crc);
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igt_plane_set_fb(primary, NULL);
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igt_display_commit(&data->display);
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igt_remove_fb(data->drm_fd, &red_fb);
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igt_remove_fb(data->drm_fd, &green_fb);
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igt_remove_fb(data->drm_fd, &blue_fb);
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igt_pipe_crc_free(data->pipe_crc);
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data->pipe_crc = NULL;
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igt_output_set_pipe(output, PIPE_ANY);
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igt_display_commit(&data->display);
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igt_assert(igt_crc_equal(&ref_crc, &crc));
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return true;
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}
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/*
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* 1. set primary plane to full red
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* 2. grab a reference crc
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* 3. set primary plane to full green
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* 4. wait for vblank
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* 5. pan primary plane a bit (to cause a mmio flip w/o vblank wait)
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* 6. queue lots of GPU activity to delay the subsequent page flip
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* 6. queue a page flip to a blue fb
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* 7. set primary plane to red fb
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* 8. wait for GPU to finish
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* 9. compare current crc with reference crc
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*
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* We expect the primary plane to display full red at the end.
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* If the previously schedule primary plane pan operation has interfered
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* with the following page flip, the driver may have mistakenly completed
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* the flip before it was executed by the CS, and hence the subsequent mmio
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* flips may have overtaken it. So once we've finished everything
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* the CS flip may have been the last thing to occur, which means
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* the primary plane may be full blue instead of the red it's
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* supposed to be.
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*/
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static bool
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test_crtc(data_t *data, igt_output_t *output, enum pipe pipe)
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{
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struct igt_fb red_fb, green_fb, blue_fb;
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drmModeModeInfo *mode;
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igt_plane_t *primary;
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igt_crc_t ref_crc, crc;
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int ret;
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igt_output_set_pipe(output, pipe);
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igt_display_commit(&data->display);
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if (!output->valid) {
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igt_output_set_pipe(output, PIPE_ANY);
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igt_display_commit(&data->display);
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return false;
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}
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primary = igt_output_get_plane(output, 0);
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mode = igt_output_get_mode(output);
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igt_create_color_fb(data->drm_fd, mode->hdisplay, mode->vdisplay+1,
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DRM_FORMAT_XRGB8888,
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false, /* tiled */
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1.0, 0.0, 0.0,
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&red_fb);
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igt_create_color_fb(data->drm_fd, mode->hdisplay, mode->vdisplay+1,
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DRM_FORMAT_XRGB8888,
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false, /* tiled */
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0.0, 0.0, 1.0,
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&blue_fb);
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igt_create_color_fb(data->drm_fd, mode->hdisplay, mode->vdisplay+1,
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DRM_FORMAT_XRGB8888,
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false, /* tiled */
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0.0, 1.0, 0.0,
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&green_fb);
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/*
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* Make sure these buffers are suited for display use
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* because most of the modeset operations must be fast
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* later on.
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*/
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igt_plane_set_fb(primary, &green_fb);
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igt_display_commit(&data->display);
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igt_plane_set_fb(primary, &blue_fb);
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igt_display_commit(&data->display);
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if (data->pipe_crc)
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igt_pipe_crc_free(data->pipe_crc);
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data->pipe_crc = igt_pipe_crc_new(pipe, INTEL_PIPE_CRC_SOURCE_AUTO);
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if (!data->pipe_crc) {
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igt_info("auto crc not supported on this connector with crtc %i\n",
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pipe);
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igt_plane_set_fb(primary, NULL);
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igt_output_set_pipe(output, PIPE_ANY);
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igt_display_commit(&data->display);
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igt_remove_fb(data->drm_fd, &red_fb);
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igt_remove_fb(data->drm_fd, &green_fb);
|
||||
igt_remove_fb(data->drm_fd, &blue_fb);
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
/* set red fb and grab reference crc */
|
||||
igt_plane_set_fb(primary, &red_fb);
|
||||
igt_display_commit(&data->display);
|
||||
igt_pipe_crc_collect_crc(data->pipe_crc, &ref_crc);
|
||||
|
||||
/*
|
||||
* Further down we need to issue an mmio flip w/o the kernel
|
||||
* waiting for vblank. The easiest way is to just pan within
|
||||
* the same FB. So pan away a bit here, and later we undo this
|
||||
* with another pan which will result in the desired mmio flip.
|
||||
*/
|
||||
ret = drmModeSetCrtc(data->drm_fd, output->config.crtc->crtc_id,
|
||||
green_fb.fb_id, 0, 1, &output->id, 1,
|
||||
mode);
|
||||
igt_assert(ret == 0);
|
||||
|
||||
/*
|
||||
* Make it more likely that the CS flip has been submitted into the
|
||||
* ring by the time the mmio flip from the drmModeSetCrtc() below
|
||||
* completes. The driver will then mistake the flip done interrupt
|
||||
* from the mmio flip as the flip done interrupt from the CS flip.
|
||||
*/
|
||||
igt_wait_for_vblank(data->drm_fd, pipe);
|
||||
|
||||
/* now issue the mmio flip w/o vblank waits in the kernel, ie. pan a bit */
|
||||
ret = drmModeSetCrtc(data->drm_fd, output->config.crtc->crtc_id,
|
||||
green_fb.fb_id, 0, 0, &output->id, 1,
|
||||
mode);
|
||||
igt_assert(ret == 0);
|
||||
|
||||
make_gpu_busy(data, blue_fb.gem_handle);
|
||||
|
||||
/*
|
||||
* Submit the CS flip. The commands must be emitted into the ring
|
||||
* before the mmio flip from the panning operation completes.
|
||||
*/
|
||||
data->flip_done = false;
|
||||
ret = drmModePageFlip(data->drm_fd, output->config.crtc->crtc_id,
|
||||
blue_fb.fb_id, DRM_MODE_PAGE_FLIP_EVENT, data);
|
||||
igt_assert(ret == 0);
|
||||
|
||||
/*
|
||||
* Set primary plane to red fb. This should wait for the CS flip
|
||||
* to complete. But if the kernel mistook the flip done interrupt
|
||||
* from the mmio flip as the flip done from the CS flip, this will
|
||||
* not wait for anything. And hence the the CS flip will actually
|
||||
* occur after this mmio flip.
|
||||
*/
|
||||
ret = drmModeSetCrtc(data->drm_fd, output->config.crtc->crtc_id,
|
||||
red_fb.fb_id, 0, 0, &output->id, 1,
|
||||
mode);
|
||||
igt_assert(ret == 0);
|
||||
|
||||
/* Make sure the flip has been executed */
|
||||
wait_for_flip(data, blue_fb.gem_handle);
|
||||
|
||||
/* Grab crc and compare with the extected result */
|
||||
igt_pipe_crc_collect_crc(data->pipe_crc, &crc);
|
||||
|
||||
igt_plane_set_fb(primary, NULL);
|
||||
igt_display_commit(&data->display);
|
||||
|
||||
igt_remove_fb(data->drm_fd, &red_fb);
|
||||
igt_remove_fb(data->drm_fd, &green_fb);
|
||||
igt_remove_fb(data->drm_fd, &blue_fb);
|
||||
|
||||
igt_pipe_crc_free(data->pipe_crc);
|
||||
data->pipe_crc = NULL;
|
||||
|
||||
igt_output_set_pipe(output, PIPE_ANY);
|
||||
igt_display_commit(&data->display);
|
||||
|
||||
igt_assert(igt_crc_equal(&ref_crc, &crc));
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static void
|
||||
run_plane_test_for_pipe(data_t *data, enum pipe pipe)
|
||||
{
|
||||
igt_output_t *output;
|
||||
enum igt_plane plane = 1; /* testing with one sprite is enough */
|
||||
int valid_tests = 0;
|
||||
|
||||
igt_require(data->display.pipes[pipe].n_planes > 2);
|
||||
|
||||
for_each_connected_output(&data->display, output) {
|
||||
if (test_plane(data, output, pipe, plane))
|
||||
valid_tests++;
|
||||
}
|
||||
|
||||
igt_require_f(valid_tests, "no valid crtc/connector combinations found\n");
|
||||
}
|
||||
|
||||
static void
|
||||
run_crtc_test_for_pipe(data_t *data, enum pipe pipe)
|
||||
{
|
||||
igt_output_t *output;
|
||||
int valid_tests = 0;
|
||||
|
||||
for_each_connected_output(&data->display, output) {
|
||||
if (test_crtc(data, output, pipe))
|
||||
valid_tests++;
|
||||
}
|
||||
|
||||
igt_require_f(valid_tests, "no valid crtc/connector combinations found\n");
|
||||
}
|
||||
|
||||
static data_t data;
|
||||
|
||||
igt_main
|
||||
{
|
||||
int pipe;
|
||||
|
||||
igt_skip_on_simulation();
|
||||
|
||||
igt_fixture {
|
||||
data.drm_fd = drm_open_any();
|
||||
|
||||
igt_set_vt_graphics_mode();
|
||||
|
||||
data.devid = intel_get_drm_devid(data.drm_fd);
|
||||
|
||||
igt_require_pipe_crc();
|
||||
igt_display_init(&data.display, data.drm_fd);
|
||||
|
||||
data.bufmgr = drm_intel_bufmgr_gem_init(data.drm_fd, 4096);
|
||||
igt_assert(data.bufmgr);
|
||||
drm_intel_bufmgr_gem_enable_reuse(data.bufmgr);
|
||||
|
||||
data.busy_bo = drm_intel_bo_alloc(data.bufmgr, "bo",
|
||||
64*1024*1024, 4096);
|
||||
gem_set_tiling(data.drm_fd, data.busy_bo->handle, 0, 4096);
|
||||
}
|
||||
|
||||
igt_subtest_f("setplane_vs_cs_flip") {
|
||||
for (pipe = 0; pipe < data.display.n_pipes; pipe++)
|
||||
run_plane_test_for_pipe(&data, pipe);
|
||||
}
|
||||
|
||||
igt_subtest_f("setcrtc_vs_cs_flip") {
|
||||
for (pipe = 0; pipe < data.display.n_pipes; pipe++)
|
||||
run_crtc_test_for_pipe(&data, pipe);
|
||||
}
|
||||
|
||||
igt_fixture {
|
||||
drm_intel_bo_unreference(data.busy_bo);
|
||||
drm_intel_bufmgr_destroy(data.bufmgr);
|
||||
igt_display_fini(&data.display);
|
||||
}
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user