mirror of
https://github.com/tiagovignatti/intel-gpu-tools.git
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assembler: Add error() and warn() shorthands and use them in set_src[01]
Now that we have locations, we can write error() and warn() functions giving more information about where it's going wrong. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
This commit is contained in:
Damien Lespiau
parent
d94e8a6cf0
commit
e9172aa225
@ -69,6 +69,8 @@ typedef struct { \
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/* ensure nobody changes the size of struct brw_instruction */
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STRUCT_SIZE_ASSERT(brw_instruction, 16);
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#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
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struct condition {
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int cond;
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int flag_reg_nr;
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121
assembler/gram.y
121
assembler/gram.y
@ -30,6 +30,7 @@
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#include <string.h>
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#include <stdlib.h>
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#include <stdbool.h>
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#include <stdarg.h>
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#include <assert.h>
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#include "gen4asm.h"
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#include "brw_eu.h"
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@ -39,6 +40,15 @@
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#define SWIZZLE(reg) (reg.dw1.bits.swizzle)
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#define YYLTYPE YYLTYPE
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typedef struct YYLTYPE
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{
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int first_line;
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int first_column;
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int last_line;
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int last_column;
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} YYLTYPE;
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extern long int gen_level;
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extern int advanced_flag;
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extern int yylineno;
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@ -76,9 +86,11 @@ static int get_type_size(GLuint type);
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int set_instruction_dest(struct brw_instruction *instr,
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struct brw_reg *dest);
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int set_instruction_src0(struct brw_instruction *instr,
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struct src_operand *src);
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struct src_operand *src,
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YYLTYPE *location);
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int set_instruction_src1(struct brw_instruction *instr,
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struct src_operand *src);
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struct src_operand *src,
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YYLTYPE *location);
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int set_instruction_dest_three_src(struct brw_instruction *instr,
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struct brw_reg *dest);
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int set_instruction_src0_three_src(struct brw_instruction *instr,
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@ -96,6 +108,31 @@ void set_direct_dst_operand(struct brw_reg *dst, struct brw_reg *reg,
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void set_direct_src_operand(struct src_operand *src, struct brw_reg *reg,
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int type);
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enum message_level {
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WARN,
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ERROR,
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};
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static void message(enum message_level level, YYLTYPE *location,
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const char *fmt, ...)
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{
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static const char *level_str[] = { "warning", "error" };
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va_list args;
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if (location)
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fprintf(stderr, "%d:%d: %s: ", location->first_line,
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location->first_column, level_str[level]);
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else
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fprintf(stderr, "%s: ", level_str[level]);
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va_start(args, fmt);
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vfprintf(stderr, fmt, args);
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va_end(args);
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}
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#define warn(l, fmt, ...) message(WARN, location, fmt, ## __VA_ARGS__)
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#define error(l, fmt, ...) message(ERROR, location, fmt, ## __VA_ARGS__)
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/* like strcmp, but handles NULL pointers */
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static bool strcmp0(const char *s1, const char* s2)
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{
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@ -214,7 +251,9 @@ static bool validate_dst_reg(struct brw_instruction *insn, struct brw_reg *reg)
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return true;
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}
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static bool validate_src_reg(struct brw_instruction *insn, struct brw_reg reg)
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static bool validate_src_reg(struct brw_instruction *insn,
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struct brw_reg reg,
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YYLTYPE *location)
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{
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if (reg.file == BRW_IMMEDIATE_VALUE)
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return true;
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@ -222,7 +261,7 @@ static bool validate_src_reg(struct brw_instruction *insn, struct brw_reg reg)
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if (insn->header.access_mode == BRW_ALIGN_1 &&
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SWIZZLE(reg) && SWIZZLE(reg) != BRW_SWIZZLE_NOOP)
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{
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fprintf(stderr, "error: swizzle bits set in align1 instruction\n");
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error(location, "swizzle bits set in align1 instruction\n");
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return false;
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}
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@ -630,8 +669,8 @@ ifelseinstruction: ENDIF
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$$.gen.header.thread_control |= BRW_THREAD_SWITCH;
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ip_dst.width = $2;
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set_instruction_dest(&$$.gen, &ip_dst);
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set_instruction_src0(&$$.gen, &ip_src);
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set_instruction_src1(&$$.gen, &$3);
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set_instruction_src0(&$$.gen, &ip_src, NULL);
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set_instruction_src1(&$$.gen, &$3, NULL);
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$$.first_reloc_target = $3.reloc_target;
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$$.first_reloc_offset = $3.imm32;
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} else if(IS_GENp(6)) {
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@ -666,8 +705,8 @@ ifelseinstruction: ENDIF
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$$.gen.header.thread_control |= BRW_THREAD_SWITCH;
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ip_dst.width = $3;
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set_instruction_dest(&$$.gen, &ip_dst);
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set_instruction_src0(&$$.gen, &ip_src);
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set_instruction_src1(&$$.gen, &$4);
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set_instruction_src0(&$$.gen, &ip_src, NULL);
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set_instruction_src1(&$$.gen, &$4, NULL);
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}
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$$.first_reloc_target = $4.reloc_target;
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$$.first_reloc_offset = $4.imm32;
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@ -704,8 +743,8 @@ loopinstruction: predicate WHILE execsize relativelocation instoptions
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set_instruction_predicate(&$$.gen, &$1);
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$$.gen.header.opcode = $2;
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$$.gen.header.thread_control |= BRW_THREAD_SWITCH;
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set_instruction_src0(&$$.gen, &ip_src);
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set_instruction_src1(&$$.gen, &$4);
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set_instruction_src0(&$$.gen, &ip_src, NULL);
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set_instruction_src1(&$$.gen, &$4, NULL);
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$$.first_reloc_target = $4.reloc_target;
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$$.first_reloc_offset = $4.imm32;
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} else if (IS_GENp(6)) {
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@ -743,7 +782,7 @@ haltinstruction: predicate HALT execsize relativelocation relativelocation insto
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$$.second_reloc_offset = $5.imm32;
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dst_null_reg.width = $3;
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set_instruction_dest(&$$.gen, &dst_null_reg);
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set_instruction_src0(&$$.gen, &src_null_reg);
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set_instruction_src0(&$$.gen, &src_null_reg, NULL);
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};
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multibranchinstruction:
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@ -772,7 +811,7 @@ multibranchinstruction:
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$$.second_reloc_offset = $5.imm32;
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dst_null_reg.width = $3;
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set_instruction_dest(&$$.gen, &dst_null_reg);
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set_instruction_src0(&$$.gen, &src_null_reg);
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set_instruction_src0(&$$.gen, &src_null_reg, NULL);
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}
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;
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@ -808,7 +847,7 @@ subroutineinstruction:
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src0.reg.hstride = 1; /*encoded 1*/
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src0.reg.width = 1; /*encoded 2*/
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src0.reg.vstride = 2; /*encoded 2*/
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set_instruction_src0(&$$.gen, &src0);
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set_instruction_src0(&$$.gen, &src0, NULL);
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$$.first_reloc_target = $5.reloc_target;
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$$.first_reloc_offset = $5.imm32;
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@ -830,7 +869,7 @@ subroutineinstruction:
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$5.reg.hstride = 1; /*encoded 1*/
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$5.reg.width = 1; /*encoded 2*/
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$5.reg.vstride = 2; /*encoded 2*/
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set_instruction_src0(&$$.gen, &$5);
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set_instruction_src0(&$$.gen, &$5, NULL);
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}
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;
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@ -847,7 +886,7 @@ unaryinstruction:
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set_instruction_predicate(&$$, &$1);
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if (set_instruction_dest(&$$, &$6) != 0)
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YYERROR;
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if (set_instruction_src0(&$$, &$7) != 0)
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if (set_instruction_src0(&$$, &$7, &@7) != 0)
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YYERROR;
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if ($3.flag_subreg_nr != -1) {
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@ -884,9 +923,9 @@ binaryinstruction:
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$6.width = $5;
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if (set_instruction_dest(&$$, &$6) != 0)
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YYERROR;
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if (set_instruction_src0(&$$, &$7) != 0)
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if (set_instruction_src0(&$$, &$7, &@7) != 0)
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YYERROR;
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if (set_instruction_src1(&$$, &$8) != 0)
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if (set_instruction_src1(&$$, &$8, &@8) != 0)
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YYERROR;
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if ($3.flag_subreg_nr != -1) {
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@ -923,9 +962,9 @@ binaryaccinstruction:
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set_instruction_predicate(&$$, &$1);
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if (set_instruction_dest(&$$, &$6) != 0)
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YYERROR;
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if (set_instruction_src0(&$$, &$7) != 0)
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if (set_instruction_src0(&$$, &$7, &@7) != 0)
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YYERROR;
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if (set_instruction_src1(&$$, &$8) != 0)
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if (set_instruction_src1(&$$, &$8, &@8) != 0)
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YYERROR;
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if ($3.flag_subreg_nr != -1) {
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@ -1020,9 +1059,9 @@ sendinstruction: predicate SEND execsize exp post_dst payload msgtarget
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src0.reg.type = BRW_REGISTER_TYPE_D;
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src0.reg.nr = $4;
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src0.reg.subnr = 0;
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set_instruction_src0(&$$, &src0);
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set_instruction_src0(&$$, &src0, NULL);
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} else {
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if (set_instruction_src0(&$$, &$6) != 0)
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if (set_instruction_src0(&$$, &$6, &@6) != 0)
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YYERROR;
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}
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@ -1063,10 +1102,10 @@ sendinstruction: predicate SEND execsize exp post_dst payload msgtarget
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$4.width = $3;
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if (set_instruction_dest(&$$, &$4) != 0)
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YYERROR;
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if (set_instruction_src0(&$$, &$6) != 0)
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if (set_instruction_src0(&$$, &$6, &@6) != 0)
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YYERROR;
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/* XXX is this correct? */
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if (set_instruction_src1(&$$, &$7) != 0)
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if (set_instruction_src1(&$$, &$7, &@7) != 0)
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YYERROR;
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}
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@ -1086,7 +1125,7 @@ sendinstruction: predicate SEND execsize exp post_dst payload msgtarget
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$4.width = $3;
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if (set_instruction_dest(&$$, &$4) != 0)
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YYERROR;
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if (set_instruction_src0(&$$, &$6) != 0)
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if (set_instruction_src0(&$$, &$6, &@6) != 0)
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YYERROR;
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$$.bits1.da1.src1_reg_file = BRW_IMMEDIATE_VALUE;
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$$.bits1.da1.src1_reg_type = $7.reg.type;
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@ -1130,7 +1169,7 @@ sendinstruction: predicate SEND execsize exp post_dst payload msgtarget
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src0.reg.nr = $5.nr;
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src0.reg.subnr = 0;
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set_instruction_src0(&$$, &src0);
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set_instruction_src0(&$$, &src0, NULL);
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$$.bits1.da1.src1_reg_file = BRW_IMMEDIATE_VALUE;
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$$.bits1.da1.src1_reg_type = $7.reg.type;
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@ -1176,9 +1215,9 @@ sendinstruction: predicate SEND execsize exp post_dst payload msgtarget
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src0.reg.nr = $5.nr;
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src0.reg.subnr = 0;
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set_instruction_src0(&$$, &src0);
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set_instruction_src0(&$$, &src0, NULL);
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set_instruction_src1(&$$, &$7);
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set_instruction_src1(&$$, &$7, &@7);
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$$.bits3.generic_gen5.end_of_thread = !!($6 & EX_DESC_EOT_MASK);
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}
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| predicate SEND execsize dst sendleadreg payload sndopr imm32reg instoptions
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@ -1197,7 +1236,7 @@ sendinstruction: predicate SEND execsize exp post_dst payload msgtarget
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$4.width = $3;
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if (set_instruction_dest(&$$, &$4) != 0)
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YYERROR;
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if (set_instruction_src0(&$$, &$6) != 0)
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if (set_instruction_src0(&$$, &$6, &@6) != 0)
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YYERROR;
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$$.bits1.da1.src1_reg_file = BRW_IMMEDIATE_VALUE;
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$$.bits1.da1.src1_reg_type = $8.reg.type;
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@ -1220,10 +1259,10 @@ sendinstruction: predicate SEND execsize exp post_dst payload msgtarget
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$4.width = $3;
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if (set_instruction_dest(&$$, &$4) != 0)
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YYERROR;
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if (set_instruction_src0(&$$, &$6) != 0)
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if (set_instruction_src0(&$$, &$6, &@6) != 0)
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YYERROR;
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/* XXX is this correct? */
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if (set_instruction_src1(&$$, &$8) != 0)
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if (set_instruction_src1(&$$, &$8, &@8) != 0)
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YYERROR;
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if (IS_GENx(5)) {
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$$.bits2.send_gen5.sfid = $7;
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@ -1252,8 +1291,8 @@ jumpinstruction: predicate JMPI execsize relativelocation2
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set_instruction_predicate(&$$.gen, &$1);
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ip_dst.width = ffs(1) - 1;
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set_instruction_dest(&$$.gen, &ip_dst);
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set_instruction_src0(&$$.gen, &ip_src);
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set_instruction_src1(&$$.gen, &$4);
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set_instruction_src0(&$$.gen, &ip_src, NULL);
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set_instruction_src1(&$$.gen, &$4, NULL);
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$$.first_reloc_target = $4.reloc_target;
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$$.first_reloc_offset = $4.imm32;
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}
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@ -1269,9 +1308,9 @@ mathinstruction: predicate MATH_INST execsize dst src srcimm math_function insto
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$4.width = $3;
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if (set_instruction_dest(&$$, &$4) != 0)
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YYERROR;
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if (set_instruction_src0(&$$, &$5) != 0)
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if (set_instruction_src0(&$$, &$5, &@5) != 0)
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YYERROR;
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if (set_instruction_src1(&$$, &$6) != 0)
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if (set_instruction_src1(&$$, &$6, &@6) != 0)
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YYERROR;
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}
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;
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@ -1309,8 +1348,8 @@ syncinstruction: predicate WAIT notifyreg
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notify_dst.width = ffs(1) - 1;
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set_instruction_dest(&$$, ¬ify_dst);
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set_direct_src_operand(¬ify_src, &$3, BRW_REGISTER_TYPE_D);
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set_instruction_src0(&$$, ¬ify_src);
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set_instruction_src1(&$$, &src_null_reg);
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set_instruction_src0(&$$, ¬ify_src, NULL);
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set_instruction_src1(&$$, &src_null_reg, NULL);
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}
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;
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@ -2903,12 +2942,13 @@ int set_instruction_dest(struct brw_instruction *instr,
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/* Sets the first source operand for the instruction. Returns 0 on success. */
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int set_instruction_src0(struct brw_instruction *instr,
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struct src_operand *src)
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struct src_operand *src,
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YYLTYPE *location)
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{
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if (advanced_flag)
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reset_instruction_src_region(instr, src);
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if (!validate_src_reg(instr, src->reg))
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if (!validate_src_reg(instr, src->reg, location))
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return 1;
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instr->bits1.da1.src0_reg_file = src->reg.file;
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@ -2967,12 +3007,13 @@ int set_instruction_src0(struct brw_instruction *instr,
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/* Sets the second source operand for the instruction. Returns 0 on success.
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*/
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int set_instruction_src1(struct brw_instruction *instr,
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struct src_operand *src)
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struct src_operand *src,
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YYLTYPE *location)
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{
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if (advanced_flag)
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reset_instruction_src_region(instr, src);
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if (!validate_src_reg(instr, src->reg))
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if (!validate_src_reg(instr, src->reg, location))
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return 1;
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instr->bits1.da1.src1_reg_file = src->reg.file;
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