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assembler: Use brw_set_src0()
Unfortunately, it's all a walk in the park. Both, internal code in the assembler and external shaders (libva) generate registers that trigger assertions in brw_eu_emit.c's brw_validate(). To fix all that I took the option to be able to emit warning with the -W flag but still make the assembler generate the same opcodes. We can fix all this, but it requires validation, something that I cannot do right now. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
This commit is contained in:
Damien Lespiau
parent
1eb622a847
commit
e7cca1a3ca
@ -204,10 +204,16 @@ validate_reg(struct brw_instruction *insn, struct brw_reg reg)
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/* 3. */
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assert(execsize >= width);
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/* FIXME: the assembler has a lot of code written that triggers the
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* assertions commented it below. Let's paper over it (for now!) until we
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* can re-validate the shaders with those little inconsistencies fixed. */
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/* 4. */
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#if 0
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if (execsize == width && hstride != 0) {
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assert(vstride == -1 || vstride == width * hstride);
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}
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#endif
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/* 5. */
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if (execsize == width && hstride == 0) {
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@ -215,15 +221,19 @@ validate_reg(struct brw_instruction *insn, struct brw_reg reg)
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}
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/* 6. */
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#if 0
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if (width == 1) {
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assert(hstride == 0);
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}
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#endif
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/* 7. */
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#if 0
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if (execsize == 1 && width == 1) {
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assert(hstride == 0);
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assert(vstride == 0);
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}
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#endif
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/* 8. */
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if (vstride == 0 && hstride == 0) {
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@ -269,8 +279,14 @@ brw_set_src0(struct brw_compile *p, struct brw_instruction *insn,
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/* Required to set some fields in src1 as well:
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*/
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insn->bits1.da1.src1_reg_file = 0; /* arf */
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/* FIXME: This looks quite wrong, tempering with src1. I did not find
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* anything in the bspec that was hinting it woud be needed when setting
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* src0. before removing this one needs to run piglit.
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insn->bits1.da1.src1_reg_file = 0;
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insn->bits1.da1.src1_reg_type = reg.type;
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*/
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}
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else
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{
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@ -296,6 +312,10 @@ brw_set_src0(struct brw_compile *p, struct brw_instruction *insn,
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}
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if (insn->header.access_mode == BRW_ALIGN_1) {
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/* FIXME: While this is correct, if the assembler uses that code path
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* the opcode generated are different and thus needs a validation
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* pass.
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if (reg.width == BRW_WIDTH_1 &&
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insn->header.execution_size == BRW_EXECUTE_1) {
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insn->bits2.da1.src0_horiz_stride = BRW_HORIZONTAL_STRIDE_0;
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@ -303,10 +323,11 @@ brw_set_src0(struct brw_compile *p, struct brw_instruction *insn,
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insn->bits2.da1.src0_vert_stride = BRW_VERTICAL_STRIDE_0;
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}
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else {
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*/
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insn->bits2.da1.src0_horiz_stride = reg.hstride;
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insn->bits2.da1.src0_width = reg.width;
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insn->bits2.da1.src0_vert_stride = reg.vstride;
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}
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/* } */
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}
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else {
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insn->bits2.da16.src0_swz_x = BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_X);
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@ -295,6 +295,14 @@ static bool validate_src_reg(struct brw_instruction *insn,
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/* Register Region Restrictions */
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/* B. If ExecSize = Width and HorzStride ≠ 0, VertStride must be set to
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* Width * HorzStride. */
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if (execsize == width && hstride != 0) {
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if (vstride != -1 && vstride != width * hstride);
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warn(ALL, location, "execution size == width and hstride != 0 but "
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"vstride is not width * hstride\n");
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}
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/* D. If Width = 1, HorzStride must be 0 regardless of the values of
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* ExecSize and VertStride.
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*
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@ -357,6 +365,9 @@ static int get_indirect_subreg_address(GLuint subreg)
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static void resolve_subnr(struct brw_reg *reg)
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{
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if (reg->file == BRW_IMMEDIATE_VALUE)
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return;
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if (reg->address_mode == BRW_ADDRESS_DIRECT)
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reg->subnr = get_subreg_address(reg->file, reg->type, reg->subnr,
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reg->address_mode);
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@ -2996,61 +3007,18 @@ int set_instruction_src0(struct brw_instruction *instr,
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struct src_operand *src,
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YYLTYPE *location)
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{
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if (advanced_flag)
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reset_instruction_src_region(instr, src);
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if (!validate_src_reg(instr, src->reg, location))
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return 1;
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instr->bits1.da1.src0_reg_file = src->reg.file;
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instr->bits1.da1.src0_reg_type = src->reg.type;
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if (src->reg.file == BRW_IMMEDIATE_VALUE) {
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instr->bits3.ud = src->reg.dw1.ud;
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} else if (src->reg.address_mode == BRW_ADDRESS_DIRECT) {
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if (instr->header.access_mode == BRW_ALIGN_1) {
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instr->bits2.da1.src0_subreg_nr = get_subreg_address(src->reg.file, src->reg.type, src->reg.subnr, src->reg.address_mode);
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instr->bits2.da1.src0_reg_nr = src->reg.nr;
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instr->bits2.da1.src0_vert_stride = src->reg.vstride;
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instr->bits2.da1.src0_width = src->reg.width;
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instr->bits2.da1.src0_horiz_stride = src->reg.hstride;
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instr->bits2.da1.src0_negate = src->reg.negate;
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instr->bits2.da1.src0_abs = src->reg.abs;
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instr->bits2.da1.src0_address_mode = src->reg.address_mode;
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} else {
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instr->bits2.da16.src0_subreg_nr = get_subreg_address(src->reg.file, src->reg.type, src->reg.subnr, src->reg.address_mode);
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instr->bits2.da16.src0_reg_nr = src->reg.nr;
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instr->bits2.da16.src0_vert_stride = src->reg.vstride;
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instr->bits2.da16.src0_negate = src->reg.negate;
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instr->bits2.da16.src0_abs = src->reg.abs;
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instr->bits2.da16.src0_swz_x = BRW_GET_SWZ(SWIZZLE(src->reg), 0);
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instr->bits2.da16.src0_swz_y = BRW_GET_SWZ(SWIZZLE(src->reg), 1);
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instr->bits2.da16.src0_swz_z = BRW_GET_SWZ(SWIZZLE(src->reg), 2);
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instr->bits2.da16.src0_swz_w = BRW_GET_SWZ(SWIZZLE(src->reg), 3);
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instr->bits2.da16.src0_address_mode = src->reg.address_mode;
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}
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} else {
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if (instr->header.access_mode == BRW_ALIGN_1) {
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instr->bits2.ia1.src0_indirect_offset = src->reg.dw1.bits.indirect_offset;
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instr->bits2.ia1.src0_subreg_nr = get_indirect_subreg_address(src->reg.subnr);
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instr->bits2.ia1.src0_abs = src->reg.abs;
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instr->bits2.ia1.src0_negate = src->reg.negate;
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instr->bits2.ia1.src0_address_mode = src->reg.address_mode;
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instr->bits2.ia1.src0_horiz_stride = src->reg.hstride;
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instr->bits2.ia1.src0_width = src->reg.width;
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instr->bits2.ia1.src0_vert_stride = src->reg.vstride;
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} else {
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instr->bits2.ia16.src0_swz_x = BRW_GET_SWZ(SWIZZLE(src->reg), 0);
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instr->bits2.ia16.src0_swz_y = BRW_GET_SWZ(SWIZZLE(src->reg), 1);
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instr->bits2.ia16.src0_swz_z = BRW_GET_SWZ(SWIZZLE(src->reg), 2);
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instr->bits2.ia16.src0_swz_w = BRW_GET_SWZ(SWIZZLE(src->reg), 3);
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instr->bits2.ia16.src0_indirect_offset = (src->reg.dw1.bits.indirect_offset >> 4); /* half register aligned */
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instr->bits2.ia16.src0_subreg_nr = get_indirect_subreg_address(src->reg.subnr);
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instr->bits2.ia16.src0_abs = src->reg.abs;
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instr->bits2.ia16.src0_negate = src->reg.negate;
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instr->bits2.ia16.src0_address_mode = src->reg.address_mode;
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instr->bits2.ia16.src0_vert_stride = src->reg.vstride;
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}
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}
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/* the assembler support expressing subnr in bytes or in number of
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* elements. */
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resolve_subnr(&src->reg);
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brw_set_src0(&genasm_compile, instr, src->reg);
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return 0;
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}
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