assembler: Use brw_set_src0()

Unfortunately, it's all a walk in the park. Both, internal code in the
assembler and external shaders (libva) generate registers that trigger
assertions in brw_eu_emit.c's brw_validate().

To fix all that I took the option to be able to emit warning with the -W
flag but still make the assembler generate the same opcodes.

We can fix all this, but it requires validation, something that I cannot
do right now.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>

assembler/brw_eu_emit.c

@@ -204,10 +204,16 @@ validate_reg(struct brw_instruction *insn, struct brw_reg reg)
    /* 3. */
    assert(execsize >= width);
 
+   /* FIXME: the assembler has a lot of code written that triggers the
+    * assertions commented it below. Let's paper over it (for now!) until we
+    * can re-validate the shaders with those little inconsistencies fixed. */
+
    /* 4. */
+#if 0
    if (execsize == width && hstride != 0) {
       assert(vstride == -1 || vstride == width * hstride);
    }
+#endif
 
    /* 5. */
    if (execsize == width && hstride == 0) {
@@ -215,15 +221,19 @@ validate_reg(struct brw_instruction *insn, struct brw_reg reg)
    }
 
    /* 6. */
+#if 0
    if (width == 1) {
       assert(hstride == 0);
    }
+#endif
 
    /* 7. */
+#if 0
    if (execsize == 1 && width == 1) {
       assert(hstride == 0);
       assert(vstride == 0);
    }
+#endif
 
    /* 8. */
    if (vstride == 0 && hstride == 0) {
@@ -269,8 +279,14 @@ brw_set_src0(struct brw_compile *p, struct brw_instruction *insn,
    
       /* Required to set some fields in src1 as well:
        */
-      insn->bits1.da1.src1_reg_file = 0; /* arf */
+
+      /* FIXME: This looks quite wrong, tempering with src1. I did not find
+       * anything in the bspec that was hinting it woud be needed when setting
+       * src0. before removing this one needs to run piglit.
+
+      insn->bits1.da1.src1_reg_file = 0;
       insn->bits1.da1.src1_reg_type = reg.type;
+       */
    }
    else 
    {
@@ -296,6 +312,10 @@ brw_set_src0(struct brw_compile *p, struct brw_instruction *insn,
       }
 
       if (insn->header.access_mode == BRW_ALIGN_1) {
+
+	 /* FIXME: While this is correct, if the assembler uses that code path
+	  * the opcode generated are different and thus needs a validation
+	  * pass.
 	 if (reg.width == BRW_WIDTH_1 && 
 	     insn->header.execution_size == BRW_EXECUTE_1) {
 	    insn->bits2.da1.src0_horiz_stride = BRW_HORIZONTAL_STRIDE_0;
@@ -303,10 +323,11 @@ brw_set_src0(struct brw_compile *p, struct brw_instruction *insn,
 	    insn->bits2.da1.src0_vert_stride = BRW_VERTICAL_STRIDE_0;
 	 }
 	 else {
+         */
 	    insn->bits2.da1.src0_horiz_stride = reg.hstride;
 	    insn->bits2.da1.src0_width = reg.width;
 	    insn->bits2.da1.src0_vert_stride = reg.vstride;
-	 }
+     /* } */
       }
       else {
 	 insn->bits2.da16.src0_swz_x = BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_X);

assembler/gram.y

@@ -295,6 +295,14 @@ static bool validate_src_reg(struct brw_instruction *insn,
 
     /* Register Region Restrictions */
 
+    /* B. If ExecSize = Width and HorzStride ≠ 0, VertStride must be set to
+     * Width * HorzStride. */
+    if (execsize == width && hstride != 0) {
+	if (vstride != -1 && vstride != width * hstride);
+	    warn(ALL, location, "execution size == width and hstride != 0 but "
+		 "vstride is not width * hstride\n");
+    }
+
     /* D. If Width = 1, HorzStride must be 0 regardless of the values of
      * ExecSize and VertStride.
      *
@@ -357,6 +365,9 @@ static int get_indirect_subreg_address(GLuint subreg)
 
 static void resolve_subnr(struct brw_reg *reg)
 {
+   if (reg->file == BRW_IMMEDIATE_VALUE)
+	return;
+
    if (reg->address_mode == BRW_ADDRESS_DIRECT)
 	reg->subnr = get_subreg_address(reg->file, reg->type, reg->subnr,
 					reg->address_mode);
@@ -2996,61 +3007,18 @@ int set_instruction_src0(struct brw_instruction *instr,
 			 struct src_operand *src,
 			 YYLTYPE *location)
 {
+
 	if (advanced_flag)
 		reset_instruction_src_region(instr, src);
 
 	if (!validate_src_reg(instr, src->reg, location))
 		return 1;
 
-	instr->bits1.da1.src0_reg_file = src->reg.file;
+	/* the assembler support expressing subnr in bytes or in number of
-	instr->bits1.da1.src0_reg_type = src->reg.type;
+	 * elements. */
-	if (src->reg.file == BRW_IMMEDIATE_VALUE) {
+	resolve_subnr(&src->reg);
-		instr->bits3.ud = src->reg.dw1.ud;
+
-	} else if (src->reg.address_mode == BRW_ADDRESS_DIRECT) {
+	brw_set_src0(&genasm_compile, instr, src->reg);
-            if (instr->header.access_mode == BRW_ALIGN_1) {
-		instr->bits2.da1.src0_subreg_nr = get_subreg_address(src->reg.file, src->reg.type, src->reg.subnr, src->reg.address_mode);
-		instr->bits2.da1.src0_reg_nr = src->reg.nr;
-		instr->bits2.da1.src0_vert_stride = src->reg.vstride;
-		instr->bits2.da1.src0_width = src->reg.width;
-		instr->bits2.da1.src0_horiz_stride = src->reg.hstride;
-		instr->bits2.da1.src0_negate = src->reg.negate;
-		instr->bits2.da1.src0_abs = src->reg.abs;
-		instr->bits2.da1.src0_address_mode = src->reg.address_mode;
-            } else {
-		instr->bits2.da16.src0_subreg_nr = get_subreg_address(src->reg.file, src->reg.type, src->reg.subnr, src->reg.address_mode);
-		instr->bits2.da16.src0_reg_nr = src->reg.nr;
-		instr->bits2.da16.src0_vert_stride = src->reg.vstride;
-		instr->bits2.da16.src0_negate = src->reg.negate;
-		instr->bits2.da16.src0_abs = src->reg.abs;
-		instr->bits2.da16.src0_swz_x = BRW_GET_SWZ(SWIZZLE(src->reg), 0);
-		instr->bits2.da16.src0_swz_y = BRW_GET_SWZ(SWIZZLE(src->reg), 1);
-		instr->bits2.da16.src0_swz_z = BRW_GET_SWZ(SWIZZLE(src->reg), 2);
-		instr->bits2.da16.src0_swz_w = BRW_GET_SWZ(SWIZZLE(src->reg), 3);
-		instr->bits2.da16.src0_address_mode = src->reg.address_mode;
-            }
-        } else {
-            if (instr->header.access_mode == BRW_ALIGN_1) {
-		instr->bits2.ia1.src0_indirect_offset = src->reg.dw1.bits.indirect_offset;
-		instr->bits2.ia1.src0_subreg_nr = get_indirect_subreg_address(src->reg.subnr);
-		instr->bits2.ia1.src0_abs = src->reg.abs;
-		instr->bits2.ia1.src0_negate = src->reg.negate;
-		instr->bits2.ia1.src0_address_mode = src->reg.address_mode;
-		instr->bits2.ia1.src0_horiz_stride = src->reg.hstride;
-		instr->bits2.ia1.src0_width = src->reg.width;
-		instr->bits2.ia1.src0_vert_stride = src->reg.vstride;
-            } else {
-		instr->bits2.ia16.src0_swz_x = BRW_GET_SWZ(SWIZZLE(src->reg), 0);
-		instr->bits2.ia16.src0_swz_y = BRW_GET_SWZ(SWIZZLE(src->reg), 1);
-		instr->bits2.ia16.src0_swz_z = BRW_GET_SWZ(SWIZZLE(src->reg), 2);
-		instr->bits2.ia16.src0_swz_w = BRW_GET_SWZ(SWIZZLE(src->reg), 3);
-		instr->bits2.ia16.src0_indirect_offset = (src->reg.dw1.bits.indirect_offset >> 4); /* half register aligned */
-		instr->bits2.ia16.src0_subreg_nr = get_indirect_subreg_address(src->reg.subnr);
-		instr->bits2.ia16.src0_abs = src->reg.abs;
-		instr->bits2.ia16.src0_negate = src->reg.negate;
-		instr->bits2.ia16.src0_address_mode = src->reg.address_mode;
-		instr->bits2.ia16.src0_vert_stride = src->reg.vstride;
-            }
-        }
 
 	return 0;
 }