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assembler: Use brw_set_src0()

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Unfortunately, it's all a walk in the park. Both, internal code in the
assembler and external shaders (libva) generate registers that trigger
assertions in brw_eu_emit.c's brw_validate().

To fix all that I took the option to be able to emit warning with the -W
flag but still make the assembler generate the same opcodes.

We can fix all this, but it requires validation, something that I cannot
do right now.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
This commit is contained in:
Damien Lespiau
2013-01-27 02:06:22 +00:00
parent 1eb622a847
commit e7cca1a3ca
2 changed files with 40 additions and 51 deletions
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assembler/brw_eu_emit.c
+23 -2
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@@ -204,10 +204,16 @@ validate_reg(struct brw_instruction *insn, struct brw_reg reg)
/* 3. */
assert(execsize >= width);
/* FIXME: the assembler has a lot of code written that triggers the
* assertions commented it below. Let's paper over it (for now!) until we
* can re-validate the shaders with those little inconsistencies fixed. */
/* 4. */
#if 0
if (execsize == width && hstride != 0) {
assert(vstride == -1 || vstride == width * hstride);
}
#endif
/* 5. */
if (execsize == width && hstride == 0) {
@@ -215,15 +221,19 @@ validate_reg(struct brw_instruction *insn, struct brw_reg reg)
}
/* 6. */
#if 0
if (width == 1) {
assert(hstride == 0);
}
#endif
/* 7. */
#if 0
if (execsize == 1 && width == 1) {
assert(hstride == 0);
assert(vstride == 0);
}
#endif
/* 8. */
if (vstride == 0 && hstride == 0) {
@@ -269,8 +279,14 @@ brw_set_src0(struct brw_compile *p, struct brw_instruction *insn,
/* Required to set some fields in src1 as well:
*/
insn->bits1.da1.src1_reg_file = 0; /* arf */
/* FIXME: This looks quite wrong, tempering with src1. I did not find
* anything in the bspec that was hinting it woud be needed when setting
* src0. before removing this one needs to run piglit.
insn->bits1.da1.src1_reg_file = 0;
insn->bits1.da1.src1_reg_type = reg.type;
*/
}
else
{
@@ -296,6 +312,10 @@ brw_set_src0(struct brw_compile *p, struct brw_instruction *insn,
}
if (insn->header.access_mode == BRW_ALIGN_1) {
/* FIXME: While this is correct, if the assembler uses that code path
* the opcode generated are different and thus needs a validation
* pass.
if (reg.width == BRW_WIDTH_1 &&
insn->header.execution_size == BRW_EXECUTE_1) {
insn->bits2.da1.src0_horiz_stride = BRW_HORIZONTAL_STRIDE_0;
@@ -303,10 +323,11 @@ brw_set_src0(struct brw_compile *p, struct brw_instruction *insn,
insn->bits2.da1.src0_vert_stride = BRW_VERTICAL_STRIDE_0;
}
else {
*/
insn->bits2.da1.src0_horiz_stride = reg.hstride;
insn->bits2.da1.src0_width = reg.width;
insn->bits2.da1.src0_vert_stride = reg.vstride;
}
/* } */
}
else {
insn->bits2.da16.src0_swz_x = BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_X);