mirror of
https://github.com/tiagovignatti/intel-gpu-tools.git
synced 2025-06-10 09:26:10 +00:00
igt/gem_ringfill: Reduce ringfill to just filling the rings
The objective of this test is to check how the driver handles a full ring. To that end we need only submit enough work to fill the ring by submitting work faster than the GPU can execute it. If we are more careful in our batch construction, we can feed them much faster and achieve the same results much quicker. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Chris Wilson
parent
c4bcffcd10
commit
e180bec7bc
@ -32,108 +32,24 @@
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*/
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#include "igt.h"
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#include <stdbool.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <fcntl.h>
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#include <inttypes.h>
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#include <errno.h>
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#include <sys/stat.h>
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#include <sys/time.h>
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#include "igt_gt.h"
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#include <drm.h>
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struct bo {
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const char *ring;
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drm_intel_bo *src, *dst, *tmp;
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};
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static const int width = 512, height = 512;
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int fd;
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static void create_bo(drm_intel_bufmgr *bufmgr,
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struct bo *b,
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const char *ring)
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static void check_bo(int fd, uint32_t handle)
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{
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int size = 4 * width * height, i;
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uint32_t *map;
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b->ring = ring;
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b->src = drm_intel_bo_alloc(bufmgr, "src", size, 4096);
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b->dst = drm_intel_bo_alloc(bufmgr, "dst", size, 4096);
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b->tmp = drm_intel_bo_alloc(bufmgr, "tmp", size, 4096);
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/* Fill the src with indexes of the pixels */
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drm_intel_bo_map(b->src, true);
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map = b->src->virtual;
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for (i = 0; i < width * height; i++)
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map[i] = i;
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drm_intel_bo_unmap(b->src);
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/* Fill the dst with garbage. */
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drm_intel_bo_map(b->dst, true);
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map = b->dst->virtual;
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for (i = 0; i < width * height; i++)
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map[i] = 0xd0d0d0d0;
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drm_intel_bo_unmap(b->dst);
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}
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static int check_bo(struct bo *b)
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{
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const uint32_t *map;
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int i, fails = 0;
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igt_debug("verifying\n");
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do_or_die(drm_intel_bo_map(b->dst, false));
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map = b->dst->virtual;
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for (i = 0; i < width*height; i++) {
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if (map[i] != i && ++fails <= 9) {
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int x = i % width;
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int y = i / width;
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igt_info("%s: copy #%d at %d,%d failed: read 0x%08x\n",
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b->ring, i, x, y, map[i]);
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}
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}
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drm_intel_bo_unmap(b->dst);
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return fails;
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}
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static void destroy_bo(struct bo *b)
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{
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drm_intel_bo_unreference(b->src);
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drm_intel_bo_unreference(b->tmp);
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drm_intel_bo_unreference(b->dst);
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}
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static void fill_ring(drm_intel_bufmgr *bufmgr,
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const char *ring,
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igt_render_copyfunc_t copy)
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{
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struct intel_batchbuffer *batch;
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struct igt_buf src, tmp, dst;
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struct bo bo;
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int i;
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batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
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igt_assert(batch);
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igt_debug("Verifying result\n");
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map = gem_mmap__cpu(fd, handle, 0, 4096, PROT_READ);
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gem_set_domain(fd, handle, I915_GEM_DOMAIN_CPU, 0);
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for (i = 0; i < 1024; i++)
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igt_assert_eq(map[i], i);
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munmap(map, 4096);
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}
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create_bo(bufmgr, &bo, ring);
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src.stride = 4 * width;
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src.tiling = 0;
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src.size = 4 * width * height;
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src.num_tiles = 4 * width * height;
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dst = tmp = src;
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src.bo = bo.src;
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tmp.bo = bo.tmp;
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dst.bo = bo.dst;
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static void fill_ring(int fd, struct drm_i915_gem_execbuffer2 *execbuf)
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{
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int i;
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/* The ring we've been using is 128k, and each rendering op
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* will use at least 8 dwords:
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@ -150,120 +66,168 @@ static void fill_ring(drm_intel_bufmgr *bufmgr,
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* So iterate just a little more than that -- if we don't fill the ring
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* doing this, we aren't likely to with this test.
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*/
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for (i = 0; i < width * height; i++) {
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int x = i % width;
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int y = i / width;
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igt_assert_lt(y, height);
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/* Dummy load to fill the ring */
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copy(batch, NULL, &src, 0, 0, width, height, &tmp, 0, 0);
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/* And copy the src into dst, pixel by pixel */
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copy(batch, NULL, &src, x, y, 1, 1, &dst, x, y);
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}
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/* verify */
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igt_assert_eq(check_bo(&bo), 0);
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destroy_bo(&bo);
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intel_batchbuffer_free(batch);
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igt_debug("Executing execbuf %d times\n", 128*1024/(8*4));
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for (i = 0; i < 128*1024 / (8 * 4); i++)
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gem_execbuf(fd, execbuf);
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}
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static void blt_copy(struct intel_batchbuffer *batch,
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drm_intel_context *context,
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struct igt_buf *src, unsigned src_x, unsigned src_y,
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unsigned w, unsigned h,
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struct igt_buf *dst, unsigned dst_x, unsigned dst_y)
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static int __gem_execbuf(int fd, struct drm_i915_gem_execbuffer2 *execbuf)
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{
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BLIT_COPY_BATCH_START(0);
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OUT_BATCH((3 << 24) | /* 32 bits */
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(0xcc << 16) | /* copy ROP */
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dst->stride);
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OUT_BATCH((dst_y << 16) | dst_x); /* dst x1,y1 */
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OUT_BATCH(((dst_y + h) << 16) | (dst_x + w)); /* dst x2,y2 */
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OUT_RELOC_FENCED(dst->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
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OUT_BATCH((src_y << 16) | src_x); /* src x1,y1 */
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OUT_BATCH(src->stride);
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OUT_RELOC_FENCED(src->bo, I915_GEM_DOMAIN_RENDER, 0, 0);
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ADVANCE_BATCH();
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intel_batchbuffer_flush(batch);
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int err = 0;
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if (drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, execbuf))
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err = -errno;
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return err;
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}
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static void run_test(int ring, bool interruptible, int nchild) {
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drm_intel_bufmgr *bufmgr;
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igt_render_copyfunc_t copy;
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const char* ring_name;
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#define INTERRUPTIBLE 0x1
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#define HANG 0x2
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#define CHILD 0x8
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#define FORKED 0x8
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#define BOMB 0x10
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bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
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igt_assert(bufmgr);
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drm_intel_bufmgr_gem_enable_reuse(bufmgr);
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static void run_test(int fd, unsigned ring, unsigned flags)
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{
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const int gen = intel_gen(intel_get_drm_devid(fd));
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const uint32_t bbe = MI_BATCH_BUFFER_END;
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struct drm_i915_gem_exec_object2 obj[2];
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struct drm_i915_gem_relocation_entry reloc[1024];
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struct drm_i915_gem_execbuffer2 execbuf;
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struct igt_hang_ring hang;
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uint32_t *batch, *b;
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int i;
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if (ring == I915_EXEC_RENDER) {
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copy = igt_get_render_copyfunc(intel_get_drm_devid(fd));
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ring_name = "render";
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} else if (ring == I915_EXEC_BLT) {
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copy = blt_copy;
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ring_name = "blt";
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} else {
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igt_fail_on_f(true, "Unsupported ring.");
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}
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memset(&execbuf, 0, sizeof(execbuf));
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execbuf.buffers_ptr = (uintptr_t)obj;
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execbuf.buffer_count = 2;
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execbuf.flags = ring | (1 << 11);
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/* Not all platforms have dedicated render ring. */
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igt_require(copy);
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memset(obj, 0, sizeof(obj));
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obj[0].handle = gem_create(fd, 4096);
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obj[1].handle = gem_create(fd, 1024*16 + 4096);
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gem_write(fd, obj[1].handle, 0, &bbe, sizeof(bbe));
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igt_require(__gem_execbuf(fd, &execbuf) == 0);
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if (interruptible) {
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igt_fork_signal_helper();
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}
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obj[1].relocs_ptr = (uintptr_t)reloc;
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obj[1].relocation_count = 1024;
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if (nchild) {
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igt_fork(child, nchild) {
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fill_ring(bufmgr, ring_name, copy);
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batch = gem_mmap__cpu(fd, obj[1].handle, 0, 16*1024 + 4096,
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PROT_WRITE | PROT_READ);
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gem_set_domain(fd, obj[1].handle,
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I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
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memset(reloc, 0, sizeof(reloc));
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b = batch;
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for (i = 0; i < 1024; i++) {
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uint64_t offset;
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reloc[i].target_handle = obj[0].handle;
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reloc[i].offset = (b - batch + 1) * sizeof(*batch);
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reloc[i].presumed_offset = obj[0].offset;
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reloc[i].delta = i * sizeof(uint32_t);
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reloc[i].read_domains = I915_GEM_DOMAIN_INSTRUCTION;
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reloc[i].write_domain = I915_GEM_DOMAIN_INSTRUCTION;
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offset = obj[0].offset + reloc[i].delta;
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*b++ = MI_STORE_DWORD_IMM;
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if (gen >= 8) {
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*b++ = offset;
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*b++ = offset >> 32;
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} else if (gen >= 4) {
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*b++ = 0;
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*b++ = offset;
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reloc[i].offset += sizeof(*batch);
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} else {
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*b++ = offset;
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}
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*b++ = i;
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}
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*b++ = MI_BATCH_BUFFER_END;
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munmap(batch, 16*1024+4096);
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gem_execbuf(fd, &execbuf);
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memset(&hang, 0, sizeof(hang));
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if (flags & HANG)
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hang = igt_hang_ring(fd, ring & ~(3<<13));
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if (flags & INTERRUPTIBLE)
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igt_fork_signal_helper();
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if (flags & (CHILD | FORKED | BOMB)) {
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int nchild;
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if (flags & CHILD)
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nchild = 1;
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else if (flags & FORKED)
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nchild = sysconf(_SC_NPROCESSORS_ONLN);
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else
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nchild = 8*sysconf(_SC_NPROCESSORS_ONLN);
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igt_debug("Forking %d children\n", nchild);
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igt_fork(child, nchild)
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fill_ring(fd, &execbuf);
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igt_waitchildren();
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} else {
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fill_ring(bufmgr, ring_name, copy);
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}
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} else
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fill_ring(fd, &execbuf);
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if (interruptible) {
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if (flags & INTERRUPTIBLE)
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igt_stop_signal_helper();
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}
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drm_intel_bufmgr_destroy(bufmgr);
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if (flags & HANG)
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igt_post_hang_ring(fd, hang);
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else
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check_bo(fd, obj[0].handle);
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gem_close(fd, obj[1].handle);
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gem_close(fd, obj[0].handle);
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}
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igt_main
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{
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const struct {
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const char *prefix;
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const char *suffix;
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unsigned flags;
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} modes[] = {
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{ "basic-", "", 0 },
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{ "", "-interuptible", INTERRUPTIBLE },
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{ "", "-hang", HANG },
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{ "", "-child", CHILD },
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{ "", "-forked", FORKED },
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{ "", "-bomb", BOMB | INTERRUPTIBLE },
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{ NULL, NULL, 0 }
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}, *mode;
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const struct {
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const char *name;
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unsigned int flags;
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} rings[] = {
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{ "default", I915_EXEC_DEFAULT },
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{ "rcs", I915_EXEC_RENDER },
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{ "bcs", I915_EXEC_BLT },
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{ "bsd", I915_EXEC_BSD },
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{ "bsd1", I915_EXEC_BSD | 1 << 13 },
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{ "bsd2", I915_EXEC_BSD | 2 << 13 },
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{ "vebox", I915_EXEC_VEBOX },
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{ NULL, 0 }
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}, *ring;
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int fd;
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igt_skip_on_simulation();
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igt_fixture {
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igt_fixture
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fd = drm_open_driver(DRIVER_INTEL);
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for (mode = modes; mode->prefix; mode++) {
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for (ring = rings; ring->name; ring++) {
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gem_quiescent_gpu(fd);
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igt_subtest_f("%s%s%s",
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ring->flags || mode->flags ? "" : mode->prefix,
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ring->name,
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mode->suffix)
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run_test(fd, ring->flags, mode->flags);
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}
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}
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igt_subtest("blitter")
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run_test(I915_EXEC_BLT, false, 0);
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igt_subtest("render")
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run_test(I915_EXEC_RENDER, false, 0);
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igt_subtest("blitter-interruptible")
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run_test(I915_EXEC_BLT, true, 0);
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igt_subtest("render-interruptible")
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run_test(I915_EXEC_RENDER, true, 0);
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igt_subtest("blitter-forked-1")
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run_test(I915_EXEC_BLT, false, 1);
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igt_subtest("render-forked-1")
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run_test(I915_EXEC_RENDER, false, 1);
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igt_subtest("blitter-forked-4")
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run_test(I915_EXEC_BLT, false, 4);
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igt_subtest("render-forked-4")
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run_test(I915_EXEC_RENDER, false, 4);
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igt_fixture {
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igt_fixture
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close(fd);
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}
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}
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