flywithu/ntel-gpu-tools
1
0
Fork 0
mirror of https://github.com/tiagovignatti/intel-gpu-tools.git synced 2025-06-19 13:56:23 +00:00
Code Issues Releases Wiki Activity

tools/intel_reg_dumper: add some cpt/ppt debug regs

Browse Source 
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Daniel Vetter 2012-12-01 00:52:24 +01:00
parent 0d7139af58
commit da6473184c
2 changed files with 19 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
lib/intel_reg.h
View File

@ -1577,6 +1577,9 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define ADPA_HSYNC_ACTIVE_HIGH (1<<3) #define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
#define ADPA_HSYNC_ACTIVE_LOW 0 #define ADPA_HSYNC_ACTIVE_LOW 0
#define PCH_DSP_CHICKEN1 0x42000
#define PCH_DSP_CHICKEN2 0x42004
#define PCH_DSP_CHICKEN3 0x4200c
#define PCH_DSPCLK_GATE_D 0x42020 #define PCH_DSPCLK_GATE_D 0x42020
#define PCH_DSPRAMCLK_GATE_D 0x42024 #define PCH_DSPRAMCLK_GATE_D 0x42024
#define PCH_3DCGDIS0 0x46020 #define PCH_3DCGDIS0 0x46020
@ -3341,6 +3344,12 @@ typedef enum {
#define FDI_SCRAMBLING_ENABLE (0<<7) #define FDI_SCRAMBLING_ENABLE (0<<7)
#define FDI_SCRAMBLING_DISABLE (1<<7) #define FDI_SCRAMBLING_DISABLE (1<<7)
/* Additional cpu TX control regs, from ivb bspec */
#define DPAFE_BMFUNC 0x6c024
#define DPAFE_DL_IREFCAL0 0x6c02c
#define DPAFE_DL_IREFCAL1 0x6c030
#define DPAFE_DP_IREFCAL 0x6c034
/* FDI_RX, FDI_X is hard-wired to Transcoder_X */ /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
#define FDI_RXA_CTL 0xf000c #define FDI_RXA_CTL 0xf000c
#define FDI_RXB_CTL 0xf100c #define FDI_RXB_CTL 0xf100c

10
tools/intel_reg_dumper.c
View File

@ -1777,6 +1777,16 @@ static struct reg_debug ironlake_debug_regs[] = {
DEFINEREG2(FDI_RXB_CTL, ironlake_debug_fdi_rx_ctl), DEFINEREG2(FDI_RXB_CTL, ironlake_debug_fdi_rx_ctl),
DEFINEREG2(FDI_RXC_CTL, ironlake_debug_fdi_rx_ctl), DEFINEREG2(FDI_RXC_CTL, ironlake_debug_fdi_rx_ctl),
DEFINEREG(DPAFE_BMFUNC),
DEFINEREG(DPAFE_DL_IREFCAL0),
DEFINEREG(DPAFE_DL_IREFCAL1),
DEFINEREG(DPAFE_DP_IREFCAL),
DEFINEREG(PCH_DSPCLK_GATE_D),
DEFINEREG(PCH_DSP_CHICKEN1),
DEFINEREG(PCH_DSP_CHICKEN2),
DEFINEREG(PCH_DSP_CHICKEN3),
DEFINEREG2(FDI_RXA_MISC, ironlake_debug_fdi_rx_misc), DEFINEREG2(FDI_RXA_MISC, ironlake_debug_fdi_rx_misc),
DEFINEREG2(FDI_RXB_MISC, ironlake_debug_fdi_rx_misc), DEFINEREG2(FDI_RXB_MISC, ironlake_debug_fdi_rx_misc),
DEFINEREG2(FDI_RXC_MISC, ironlake_debug_fdi_rx_misc), DEFINEREG2(FDI_RXC_MISC, ironlake_debug_fdi_rx_misc),