test: Exercise concurrent GPU read/write with CPU domain access

Designed to exercise this patch to i915.ko:

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index fbf1118..57ae1f2 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3181,9 +3181,11 @@ i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_obj
        if (ret)
                return ret;

-       ret = i915_gem_object_wait_rendering(obj);
-       if (ret)
-               return ret;
+       if (write || obj->pending_gpu_write) {
+               ret = i915_gem_object_wait_rendering(obj);
+               if (ret)
+                       return ret;
+       }

        i915_gem_object_flush_gtt_write_domain(obj);

By exercising the conditions whereby should either of the checks be missed
an error is detected.

tests/.gitignore

@@ -8,6 +8,7 @@ gem_bad_blit
 gem_bad_length
 gem_basic
 gem_cs_prefetch
+gem_cpu_concurrent_blit
 gem_double_irq_loop
 gem_dummy_reloc_loop
 gem_exec_bad_domains

tests/Makefile.am

@@ -9,6 +9,7 @@ TESTS_progs = \
 	getclient \
 	getstats \
 	gem_basic \
+	gem_cpu_concurrent_blit \
 	gem_exec_nop \
 	gem_exec_blt \
 	gem_exec_bad_domains \

tests/gem_cpu_concurrent_blit.c

@@ -0,0 +1,127 @@
+/*
+ * Copyright © 2009,2012 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Eric Anholt <eric@anholt.net>
+ *    Chris Wilson <chris@chris-wilson.co.uk>
+ *
+ */
+
+/** @file gem_cpu_concurrent_blit.c
+ *
+ * This is a test of CPU read/write behavior when writing to active
+ * buffers.
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <assert.h>
+#include <fcntl.h>
+#include <inttypes.h>
+#include <errno.h>
+#include <sys/stat.h>
+#include <sys/time.h>
+#include "drm.h"
+#include "i915_drm.h"
+#include "drmtest.h"
+#include "intel_bufmgr.h"
+#include "intel_batchbuffer.h"
+#include "intel_gpu_tools.h"
+
+static void
+set_bo(drm_intel_bo *bo, uint32_t val, int width, int height)
+{
+	int size = width * height;
+	uint32_t *vaddr;
+
+	drm_intel_bo_map(bo, true);
+	vaddr = bo->virtual;
+	while (size--)
+		*vaddr++ = val;
+	drm_intel_bo_unmap(bo);
+}
+
+static void
+cmp_bo(drm_intel_bo *bo, uint32_t val, int width, int height)
+{
+	int size = width * height;
+	uint32_t *vaddr;
+
+	drm_intel_bo_map(bo, false);
+	vaddr = bo->virtual;
+	while (size--)
+		assert(*vaddr++ == val);
+	drm_intel_bo_unmap(bo);
+}
+
+static drm_intel_bo *
+create_bo(drm_intel_bufmgr *bufmgr, uint32_t val, int width, int height)
+{
+	drm_intel_bo *bo;
+
+	bo = drm_intel_bo_alloc(bufmgr, "bo", 4*width*height, 0);
+	assert(bo);
+
+	set_bo(bo, val, width, height);
+
+	return bo;
+}
+
+int
+main(int argc, char **argv)
+{
+	drm_intel_bufmgr *bufmgr;
+	struct intel_batchbuffer *batch;
+	int num_buffers = 128;
+	drm_intel_bo *src[128], *dst[128];
+	int width = 512, height = 512;
+	int fd;
+	int i;
+
+	fd = drm_open_any();
+
+	bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
+	drm_intel_bufmgr_gem_enable_reuse(bufmgr);
+	batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
+
+	for (i = 0; i < num_buffers; i++) {
+		src[i] = create_bo(bufmgr, i, width, height);
+		dst[i] = create_bo(bufmgr, ~i, width, height);
+	}
+
+	/* try to overwrite the source values */
+	for (i = 0; i < num_buffers; i++)
+		intel_copy_bo(batch, dst[i], src[i], width, height);
+	for (i = num_buffers; i--; )
+		set_bo(src[i], 0xdeadbeef, width, height);
+	for (i = 0; i < num_buffers; i++)
+		cmp_bo(dst[i], i, width, height);
+
+	/* try to read the results before the copy completes */
+	for (i = 0; i < num_buffers; i++)
+		intel_copy_bo(batch, dst[i], src[i], width, height);
+	for (i = num_buffers; i--; )
+		cmp_bo(dst[i], 0xdeadbeef, width, height);
+
+	return 0;
+}