mirror of
https://github.com/tiagovignatti/intel-gpu-tools.git
synced 2025-06-12 10:26:12 +00:00
lib: rename some power well bit names
I did the same change in the Kernel a few months ago. This should help not getting confused about which bit does what. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
This commit is contained in:
parent
3906a50ede
commit
d5cdee95d5
@ -3627,8 +3627,8 @@ typedef enum {
|
|||||||
#define HSW_PWR_WELL_CTL2 0x45404 /* Driver */
|
#define HSW_PWR_WELL_CTL2 0x45404 /* Driver */
|
||||||
#define HSW_PWR_WELL_CTL3 0x45408 /* KVMR */
|
#define HSW_PWR_WELL_CTL3 0x45408 /* KVMR */
|
||||||
#define HSW_PWR_WELL_CTL4 0x4540C /* Debug */
|
#define HSW_PWR_WELL_CTL4 0x4540C /* Debug */
|
||||||
#define HSW_PWR_WELL_ENABLE (1<<31)
|
#define HSW_PWR_WELL_ENABLE_REQUEST (1<<31)
|
||||||
#define HSW_PWR_WELL_STATE (1<<30)
|
#define HSW_PWR_WELL_STATE_ENABLED (1<<30)
|
||||||
#define HSW_PWR_WELL_CTL5 0x45410
|
#define HSW_PWR_WELL_CTL5 0x45410
|
||||||
#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31)
|
#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31)
|
||||||
#define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20)
|
#define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20)
|
||||||
|
@ -2857,12 +2857,12 @@ static uint32_t power_well_get(void)
|
|||||||
if (!IS_HASWELL(devid))
|
if (!IS_HASWELL(devid))
|
||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
ret = INREG(HSW_PWR_WELL_CTL4) & HSW_PWR_WELL_ENABLE;
|
ret = INREG(HSW_PWR_WELL_CTL4) & HSW_PWR_WELL_ENABLE_REQUEST;
|
||||||
|
|
||||||
OUTREG(HSW_PWR_WELL_CTL4, HSW_PWR_WELL_ENABLE);
|
OUTREG(HSW_PWR_WELL_CTL4, HSW_PWR_WELL_ENABLE_REQUEST);
|
||||||
|
|
||||||
for (i = 0; i < 20; i++) {
|
for (i = 0; i < 20; i++) {
|
||||||
if (INREG(HSW_PWR_WELL_CTL4) & HSW_PWR_WELL_STATE)
|
if (INREG(HSW_PWR_WELL_CTL4) & HSW_PWR_WELL_STATE_ENABLED)
|
||||||
break;
|
break;
|
||||||
usleep(1000);
|
usleep(1000);
|
||||||
}
|
}
|
||||||
|
Loading…
x
Reference in New Issue
Block a user