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tests/kms_psr_sink_crc: Fix delayed gtt/cpu write tests

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- Drop the flip from the name - we don't do that. And the blt is
  really just to have a bit of fun with the domain tracking.

- The real test is 1) dirty with gpu 2) grab 1st crc 3) set_domain for
  cpu access 4) wait a long time 5) dirty more with cpu 6) grab 2nd
  crc.

This fixes failures since with the old tests we wouldn't have noticed
the cpu rendering really.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Daniel Vetter 2014-06-17 23:47:49 +02:00
parent 838f321b9f
commit d078035ca4
1 changed files with 10 additions and 14 deletions
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24
tests/kms_psr_sink_crc.c
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@ -43,8 +43,8 @@ enum tests {
TEST_MMAP_GTT,
TEST_MMAP_GTT_NO_BUSY,
TEST_MMAP_GTT_WAITING_NO_BUSY,
TEST_SETDOMAIN_FLIP_WAIT_WRITE_GTT,
TEST_SETDOMAIN_FLIP_WAIT_WRITE_CPU,
TEST_SETDOMAIN_WAIT_WRITE_GTT,
TEST_SETDOMAIN_WAIT_WRITE_CPU,
TEST_BLT,
TEST_RENDER,
TEST_CONTEXT,
@ -82,8 +82,8 @@ static const char *tests_str(enum tests test)
[TEST_MMAP_GTT] = "mmap_gtt",
[TEST_MMAP_GTT_NO_BUSY] = "mmap_gtt_no_busy",
[TEST_MMAP_GTT_WAITING_NO_BUSY] = "mmap_gtt_waiting_no_busy",
[TEST_SETDOMAIN_FLIP_WAIT_WRITE_GTT] = "setdomain_flip_wait_write_gtt",
[TEST_SETDOMAIN_FLIP_WAIT_WRITE_CPU] = "setdomain_flip_wait_write_cpu",
[TEST_SETDOMAIN_WAIT_WRITE_GTT] = "setdomain_wait_write_gtt",
[TEST_SETDOMAIN_WAIT_WRITE_CPU] = "setdomain_wait_write_cpu",
[TEST_BLT] = "blt",
[TEST_RENDER] = "render",
[TEST_CONTEXT] = "context",
@ -386,29 +386,25 @@ static void test_crc(data_t *data)
memset(ptr, 0xff, 4);
munmap(ptr, 4096);
break;
case TEST_SETDOMAIN_FLIP_WAIT_WRITE_GTT:
case TEST_SETDOMAIN_WAIT_WRITE_GTT:
ptr = gem_mmap__gtt(data->drm_fd, handle, 4096, PROT_WRITE);
gem_set_domain(data->drm_fd, handle,
I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
igt_info("Sleeping for 10 sec...\n");
sleep(10);
fill_blt(data, handle, 0xff);
igt_assert(wait_psr_entry(data, 10));
get_sink_crc(data, ref_crc);
gem_set_domain(data->drm_fd, handle,
I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
igt_info("Sleeping for 10 sec...\n");
sleep(10);
memset(ptr, 0xff, 4);
munmap(ptr, 4096);
break;
case TEST_SETDOMAIN_FLIP_WAIT_WRITE_CPU:
case TEST_SETDOMAIN_WAIT_WRITE_CPU:
ptr = gem_mmap__cpu(data->drm_fd, handle, 4096, PROT_WRITE);
gem_set_domain(data->drm_fd, handle,
I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
igt_info("Sleeping for 10 sec...\n");
sleep(10);
fill_blt(data, handle, 0xff);
igt_assert(wait_psr_entry(data, 10));
get_sink_crc(data, ref_crc);
gem_set_domain(data->drm_fd, handle,
I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
igt_info("Sleeping for 10 sec...\n");
sleep(10);
memset(ptr, 0xff, 4);