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tests/gem_gtt_hog: Fix for BDW

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Update XY_COLOR_BLT command for Broadwell.

v2: stash devid and remove ugly double allocation. (by Chris).
v3: fix inverted blt command size and stash fd, devid and intel_gen.
v4: improved len calculation and noop between blt commands. (by Chris).

Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=73724

Cc: Chris Wilson chris@chris-wilson.co.uk>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
This commit is contained in:
Rodrigo Vivi 2014-03-18 11:18:56 -03:00 committed by Ben Widawsky
parent d8164356e7
commit cde058ae35
1 changed files with 33 additions and 19 deletions
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50
tests/gem_gtt_hog.c
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@ -44,20 +44,26 @@
static const uint32_t canary = 0xdeadbeef; static const uint32_t canary = 0xdeadbeef;
typedef struct data {
int fd;
int devid;
int intel_gen;
} data_t;
static double elapsed(const struct timeval *start, static double elapsed(const struct timeval *start,
const struct timeval *end) const struct timeval *end)
{ {
return 1e6*(end->tv_sec - start->tv_sec) + (end->tv_usec - start->tv_usec); return 1e6*(end->tv_sec - start->tv_sec) + (end->tv_usec - start->tv_usec);
} }
static void busy(int fd, uint32_t handle, int size, int loops) static void busy(data_t *data, uint32_t handle, int size, int loops)
{ {
struct drm_i915_gem_relocation_entry reloc[20]; struct drm_i915_gem_relocation_entry reloc[20];
struct drm_i915_gem_exec_object2 gem_exec[2]; struct drm_i915_gem_exec_object2 gem_exec[2];
struct drm_i915_gem_execbuffer2 execbuf; struct drm_i915_gem_execbuffer2 execbuf;
struct drm_i915_gem_pwrite gem_pwrite; struct drm_i915_gem_pwrite gem_pwrite;
struct drm_i915_gem_create create; struct drm_i915_gem_create create;
uint32_t buf[122], *b; uint32_t buf[170], *b;
int i; int i;
memset(reloc, 0, sizeof(reloc)); memset(reloc, 0, sizeof(reloc));
@ -66,7 +72,8 @@ static void busy(int fd, uint32_t handle, int size, int loops)
b = buf; b = buf;
for (i = 0; i < 20; i++) { for (i = 0; i < 20; i++) {
*b++ = XY_COLOR_BLT_CMD_NOLEN | 4 | *b++ = XY_COLOR_BLT_CMD_NOLEN |
((data->intel_gen >= 8) ? 5 : 4) |
COLOR_BLT_WRITE_ALPHA | XY_COLOR_BLT_WRITE_RGB; COLOR_BLT_WRITE_ALPHA | XY_COLOR_BLT_WRITE_RGB;
*b++ = 0xf0 << 16 | 1 << 25 | 1 << 24 | 4096; *b++ = 0xf0 << 16 | 1 << 25 | 1 << 24 | 4096;
*b++ = 0; *b++ = 0;
@ -76,9 +83,12 @@ static void busy(int fd, uint32_t handle, int size, int loops)
reloc[i].read_domains = I915_GEM_DOMAIN_RENDER; reloc[i].read_domains = I915_GEM_DOMAIN_RENDER;
reloc[i].write_domain = I915_GEM_DOMAIN_RENDER; reloc[i].write_domain = I915_GEM_DOMAIN_RENDER;
*b++ = 0; *b++ = 0;
if (data->intel_gen >= 8)
*b++ = 0;
*b++ = canary; *b++ = canary;
} }
*b++ = MI_BATCH_BUFFER_END; *b++ = MI_BATCH_BUFFER_END;
if ((b - buf) & 1)
*b++ = 0; *b++ = 0;
gem_exec[0].handle = handle; gem_exec[0].handle = handle;
@ -86,56 +96,55 @@ static void busy(int fd, uint32_t handle, int size, int loops)
create.handle = 0; create.handle = 0;
create.size = 4096; create.size = 4096;
drmIoctl(fd, DRM_IOCTL_I915_GEM_CREATE, &create); drmIoctl(data->fd, DRM_IOCTL_I915_GEM_CREATE, &create);
gem_exec[1].handle = create.handle; gem_exec[1].handle = create.handle;
gem_exec[1].relocation_count = 20; gem_exec[1].relocation_count = 20;
gem_exec[1].relocs_ptr = (uintptr_t)reloc; gem_exec[1].relocs_ptr = (uintptr_t)reloc;
execbuf.buffers_ptr = (uintptr_t)gem_exec; execbuf.buffers_ptr = (uintptr_t)gem_exec;
execbuf.buffer_count = 2; execbuf.buffer_count = 2;
execbuf.batch_len = sizeof(buf); execbuf.batch_len = (b - buf) * sizeof(buf[0]);
execbuf.flags = 1 << 11; execbuf.flags = 1 << 11;
if (HAS_BLT_RING(intel_get_drm_devid(fd))) if (HAS_BLT_RING(data->devid))
execbuf.flags |= I915_EXEC_BLT; execbuf.flags |= I915_EXEC_BLT;
gem_pwrite.handle = gem_exec[1].handle; gem_pwrite.handle = gem_exec[1].handle;
gem_pwrite.offset = 0; gem_pwrite.offset = 0;
gem_pwrite.size = sizeof(buf); gem_pwrite.size = execbuf.batch_len;
gem_pwrite.data_ptr = (uintptr_t)buf; gem_pwrite.data_ptr = (uintptr_t)buf;
if (drmIoctl(fd, DRM_IOCTL_I915_GEM_PWRITE, &gem_pwrite) == 0) { if (drmIoctl(data->fd, DRM_IOCTL_I915_GEM_PWRITE, &gem_pwrite) == 0) {
while (loops--) while (loops--)
drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf); drmIoctl(data->fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf);
} }
drmIoctl(fd, DRM_IOCTL_GEM_CLOSE, &create.handle); drmIoctl(data->fd, DRM_IOCTL_GEM_CLOSE, &create.handle);
} }
static void run(int child) static void run(data_t *data, int child)
{ {
const int size = 4096 * (256 + child * child); const int size = 4096 * (256 + child * child);
const int tiling = child % 2; const int tiling = child % 2;
const int write = child % 2; const int write = child % 2;
int fd = drm_open_any(); uint32_t handle = gem_create(data->fd, size);
uint32_t handle = gem_create(fd, size);
uint32_t *ptr; uint32_t *ptr;
uint32_t x; uint32_t x;
igt_assert(handle); igt_assert(handle);
if (tiling != I915_TILING_NONE) if (tiling != I915_TILING_NONE)
gem_set_tiling(fd, handle, tiling, 4096); gem_set_tiling(data->fd, handle, tiling, 4096);
/* load up the unfaulted bo */ /* load up the unfaulted bo */
busy(fd, handle, size, 100); busy(data, handle, size, 100);
/* Note that we ignore the API and rely on the implict /* Note that we ignore the API and rely on the implict
* set-to-gtt-domain within the fault handler. * set-to-gtt-domain within the fault handler.
*/ */
if (write) { if (write) {
ptr = gem_mmap(fd, handle, size, PROT_READ | PROT_WRITE); ptr = gem_mmap(data->fd, handle, size, PROT_READ | PROT_WRITE);
ptr[rand() % (size / 4)] = canary; ptr[rand() % (size / 4)] = canary;
} else } else
ptr = gem_mmap(fd, handle, size, PROT_READ); ptr = gem_mmap(data->fd, handle, size, PROT_READ);
x = ptr[rand() % (size / 4)]; x = ptr[rand() % (size / 4)];
munmap(ptr, size); munmap(ptr, size);
@ -147,6 +156,7 @@ igt_simple_main
{ {
struct timeval start, end; struct timeval start, end;
pid_t children[64]; pid_t children[64];
data_t data = {};
int n; int n;
/* check for an intel gpu before goint nuts. */ /* check for an intel gpu before goint nuts. */
@ -155,11 +165,15 @@ igt_simple_main
igt_skip_on_simulation(); igt_skip_on_simulation();
data.fd = drm_open_any();
data.devid = intel_get_drm_devid(data.fd);
data.intel_gen = intel_gen(data.devid);
gettimeofday(&start, NULL); gettimeofday(&start, NULL);
for (n = 0; n < ARRAY_SIZE(children); n++) { for (n = 0; n < ARRAY_SIZE(children); n++) {
switch ((children[n] = fork())) { switch ((children[n] = fork())) {
case -1: igt_assert(0); case -1: igt_assert(0);
case 0: run(n); break; case 0: run(&data, n); break;
default: break; default: break;
} }
} }