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tests/gem_gtt_hog: Fix for BDW
Update XY_COLOR_BLT command for Broadwell. v2: stash devid and remove ugly double allocation. (by Chris). v3: fix inverted blt command size and stash fd, devid and intel_gen. v4: improved len calculation and noop between blt commands. (by Chris). Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=73724 Cc: Chris Wilson chris@chris-wilson.co.uk> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
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@ -44,20 +44,26 @@
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static const uint32_t canary = 0xdeadbeef;
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typedef struct data {
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int fd;
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int devid;
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int intel_gen;
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} data_t;
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static double elapsed(const struct timeval *start,
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const struct timeval *end)
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{
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return 1e6*(end->tv_sec - start->tv_sec) + (end->tv_usec - start->tv_usec);
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}
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static void busy(int fd, uint32_t handle, int size, int loops)
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static void busy(data_t *data, uint32_t handle, int size, int loops)
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{
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struct drm_i915_gem_relocation_entry reloc[20];
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struct drm_i915_gem_exec_object2 gem_exec[2];
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struct drm_i915_gem_execbuffer2 execbuf;
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struct drm_i915_gem_pwrite gem_pwrite;
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struct drm_i915_gem_create create;
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uint32_t buf[122], *b;
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uint32_t buf[170], *b;
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int i;
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memset(reloc, 0, sizeof(reloc));
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@ -66,7 +72,8 @@ static void busy(int fd, uint32_t handle, int size, int loops)
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b = buf;
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for (i = 0; i < 20; i++) {
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*b++ = XY_COLOR_BLT_CMD_NOLEN | 4 |
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*b++ = XY_COLOR_BLT_CMD_NOLEN |
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((data->intel_gen >= 8) ? 5 : 4) |
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COLOR_BLT_WRITE_ALPHA | XY_COLOR_BLT_WRITE_RGB;
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*b++ = 0xf0 << 16 | 1 << 25 | 1 << 24 | 4096;
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*b++ = 0;
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@ -76,66 +83,68 @@ static void busy(int fd, uint32_t handle, int size, int loops)
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reloc[i].read_domains = I915_GEM_DOMAIN_RENDER;
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reloc[i].write_domain = I915_GEM_DOMAIN_RENDER;
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*b++ = 0;
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if (data->intel_gen >= 8)
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*b++ = 0;
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*b++ = canary;
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}
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*b++ = MI_BATCH_BUFFER_END;
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*b++ = 0;
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if ((b - buf) & 1)
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*b++ = 0;
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gem_exec[0].handle = handle;
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gem_exec[0].flags = EXEC_OBJECT_NEEDS_FENCE;
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create.handle = 0;
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create.size = 4096;
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drmIoctl(fd, DRM_IOCTL_I915_GEM_CREATE, &create);
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drmIoctl(data->fd, DRM_IOCTL_I915_GEM_CREATE, &create);
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gem_exec[1].handle = create.handle;
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gem_exec[1].relocation_count = 20;
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gem_exec[1].relocs_ptr = (uintptr_t)reloc;
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execbuf.buffers_ptr = (uintptr_t)gem_exec;
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execbuf.buffer_count = 2;
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execbuf.batch_len = sizeof(buf);
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execbuf.batch_len = (b - buf) * sizeof(buf[0]);
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execbuf.flags = 1 << 11;
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if (HAS_BLT_RING(intel_get_drm_devid(fd)))
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if (HAS_BLT_RING(data->devid))
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execbuf.flags |= I915_EXEC_BLT;
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gem_pwrite.handle = gem_exec[1].handle;
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gem_pwrite.offset = 0;
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gem_pwrite.size = sizeof(buf);
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gem_pwrite.size = execbuf.batch_len;
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gem_pwrite.data_ptr = (uintptr_t)buf;
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if (drmIoctl(fd, DRM_IOCTL_I915_GEM_PWRITE, &gem_pwrite) == 0) {
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if (drmIoctl(data->fd, DRM_IOCTL_I915_GEM_PWRITE, &gem_pwrite) == 0) {
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while (loops--)
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drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf);
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drmIoctl(data->fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf);
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}
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drmIoctl(fd, DRM_IOCTL_GEM_CLOSE, &create.handle);
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drmIoctl(data->fd, DRM_IOCTL_GEM_CLOSE, &create.handle);
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}
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static void run(int child)
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static void run(data_t *data, int child)
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{
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const int size = 4096 * (256 + child * child);
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const int tiling = child % 2;
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const int write = child % 2;
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int fd = drm_open_any();
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uint32_t handle = gem_create(fd, size);
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uint32_t handle = gem_create(data->fd, size);
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uint32_t *ptr;
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uint32_t x;
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igt_assert(handle);
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if (tiling != I915_TILING_NONE)
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gem_set_tiling(fd, handle, tiling, 4096);
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gem_set_tiling(data->fd, handle, tiling, 4096);
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/* load up the unfaulted bo */
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busy(fd, handle, size, 100);
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busy(data, handle, size, 100);
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/* Note that we ignore the API and rely on the implict
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* set-to-gtt-domain within the fault handler.
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*/
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if (write) {
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ptr = gem_mmap(fd, handle, size, PROT_READ | PROT_WRITE);
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ptr = gem_mmap(data->fd, handle, size, PROT_READ | PROT_WRITE);
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ptr[rand() % (size / 4)] = canary;
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} else
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ptr = gem_mmap(fd, handle, size, PROT_READ);
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ptr = gem_mmap(data->fd, handle, size, PROT_READ);
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x = ptr[rand() % (size / 4)];
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munmap(ptr, size);
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@ -147,6 +156,7 @@ igt_simple_main
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{
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struct timeval start, end;
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pid_t children[64];
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data_t data = {};
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int n;
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/* check for an intel gpu before goint nuts. */
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@ -155,11 +165,15 @@ igt_simple_main
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igt_skip_on_simulation();
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data.fd = drm_open_any();
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data.devid = intel_get_drm_devid(data.fd);
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data.intel_gen = intel_gen(data.devid);
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gettimeofday(&start, NULL);
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for (n = 0; n < ARRAY_SIZE(children); n++) {
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switch ((children[n] = fork())) {
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case -1: igt_assert(0);
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case 0: run(n); break;
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case 0: run(&data, n); break;
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default: break;
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}
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}
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