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tools/intel_display_poller: Align DSPSURF to 128k to appease gen4/vlv/chv

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gen4/vlv/chv require DSPSURF to be 128k aligned. Try to respect that
in order to avoid ugly glitches.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
This commit is contained in:
Ville Syrjälä 2015-09-09 17:00:56 +03:00
parent a8b85ea21b
commit c137ac7158
1 changed files with 3 additions and 3 deletions
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6
tools/intel_display_poller.c
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@ -314,7 +314,7 @@ static void poll_pixel_flip(uint32_t devid, int pipe, int target_pixel, int targ
break; break;
} }
write_reg(surf, saved+4096); write_reg(surf, saved+128*1024);
while (!quit){ while (!quit){
pix2 = read_reg(pix) & PIPE_PIXEL_MASK; pix2 = read_reg(pix) & PIPE_PIXEL_MASK;
@ -763,7 +763,7 @@ static void poll_dsl_flip(uint32_t devid, int pipe, int target_scanline, int tar
break; break;
} }
write_reg(surf, saved+4096); write_reg(surf, saved+128*1024);
while (!quit) { while (!quit) {
dsl2 = read_reg(dsl); dsl2 = read_reg(dsl);
@ -802,7 +802,7 @@ static void poll_dsl_surflive(uint32_t devid, int pipe,
saved = read_reg(surf); saved = read_reg(surf);
surf1 = saved & ~0xfff; surf1 = saved & ~0xfff;
surf2 = surf1 + 4096; surf2 = surf1 + 128*1024;
while (!quit) { while (!quit) {
write_reg(surf, surf2); write_reg(surf, surf2);