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assembler: Unify adding options to the header

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Right now we have duplicated code for when the option is the last in the
list or not. Put that code in a common function.

Interestingly it appears that both sides haven't been kept in sync and
that EOT and ACCWRCTRL had limitations on where they had to be in the
option list. It's fixed now!

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
This commit is contained in:
Damien Lespiau 2013-01-30 23:00:26 +00:00
parent dfe6adacc9
commit bca2ff2a02
1 changed files with 45 additions and 76 deletions
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121
assembler/gram.y
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@ -526,6 +526,49 @@ static void resolve_subnr(struct brw_reg *reg)
YYERROR; \ YYERROR; \
} while(0) } while(0)
static void add_option(struct brw_program_instruction *insn, int option)
{
switch (option) {
case ALIGN1:
GEN(insn)->header.access_mode = BRW_ALIGN_1;
break;
case ALIGN16:
GEN(insn)->header.access_mode = BRW_ALIGN_16;
break;
case SECHALF:
GEN(insn)->header.compression_control |= BRW_COMPRESSION_2NDHALF;
break;
case COMPR:
if (!IS_GENp(6))
GEN(insn)->header.compression_control |= BRW_COMPRESSION_COMPRESSED;
break;
case SWITCH:
GEN(insn)->header.thread_control |= BRW_THREAD_SWITCH;
break;
case ATOMIC:
GEN(insn)->header.thread_control |= BRW_THREAD_ATOMIC;
break;
case NODDCHK:
GEN(insn)->header.dependency_control |= BRW_DEPENDENCY_NOTCHECKED;
break;
case NODDCLR:
GEN(insn)->header.dependency_control |= BRW_DEPENDENCY_NOTCLEARED;
break;
case MASK_DISABLE:
GEN(insn)->header.mask_control = BRW_MASK_DISABLE;
break;
case BREAKPOINT:
GEN(insn)->header.debug_control = BRW_DEBUG_BREAKPOINT;
break;
case ACCWRCTRL:
GEN(insn)->header.acc_wr_control = BRW_ACCUMULATOR_WRITE_ENABLE;
break;
case EOT:
GEN(insn)->bits3.generic.end_of_thread = 1;
break;
}
}
} }
%% %%
@ -2723,86 +2766,12 @@ instoptions: /* empty */
instoption_list:instoption_list COMMA instoption instoption_list:instoption_list COMMA instoption
{ {
$$ = $1; $$ = $1;
switch ($3) { add_option(&$$, $3);
case ALIGN1:
GEN(&$$)->header.access_mode = BRW_ALIGN_1;
break;
case ALIGN16:
GEN(&$$)->header.access_mode = BRW_ALIGN_16;
break;
case SECHALF:
GEN(&$$)->header.compression_control |= BRW_COMPRESSION_2NDHALF;
break;
case COMPR:
if (!IS_GENp(6)) {
GEN(&$$)->header.compression_control |=
BRW_COMPRESSION_COMPRESSED;
}
break;
case SWITCH:
GEN(&$$)->header.thread_control |= BRW_THREAD_SWITCH;
break;
case ATOMIC:
GEN(&$$)->header.thread_control |= BRW_THREAD_ATOMIC;
break;
case NODDCHK:
GEN(&$$)->header.dependency_control |= BRW_DEPENDENCY_NOTCHECKED;
break;
case NODDCLR:
GEN(&$$)->header.dependency_control |= BRW_DEPENDENCY_NOTCLEARED;
break;
case MASK_DISABLE:
GEN(&$$)->header.mask_control = BRW_MASK_DISABLE;
break;
case BREAKPOINT:
GEN(&$$)->header.debug_control = BRW_DEBUG_BREAKPOINT;
break;
case ACCWRCTRL:
GEN(&$$)->header.acc_wr_control = BRW_ACCUMULATOR_WRITE_ENABLE;
}
} }
| instoption_list instoption | instoption_list instoption
{ {
$$ = $1; $$ = $1;
switch ($2) { add_option(&$$, $2);
case ALIGN1:
GEN(&$$)->header.access_mode = BRW_ALIGN_1;
break;
case ALIGN16:
GEN(&$$)->header.access_mode = BRW_ALIGN_16;
break;
case SECHALF:
GEN(&$$)->header.compression_control |= BRW_COMPRESSION_2NDHALF;
break;
case COMPR:
if (!IS_GENp(6)) {
GEN(&$$)->header.compression_control |=
BRW_COMPRESSION_COMPRESSED;
}
break;
case SWITCH:
GEN(&$$)->header.thread_control |= BRW_THREAD_SWITCH;
break;
case ATOMIC:
GEN(&$$)->header.thread_control |= BRW_THREAD_ATOMIC;
break;
case NODDCHK:
GEN(&$$)->header.dependency_control |= BRW_DEPENDENCY_NOTCHECKED;
break;
case NODDCLR:
GEN(&$$)->header.dependency_control |= BRW_DEPENDENCY_NOTCLEARED;
break;
case MASK_DISABLE:
GEN(&$$)->header.mask_control = BRW_MASK_DISABLE;
break;
case BREAKPOINT:
GEN(&$$)->header.debug_control = BRW_DEBUG_BREAKPOINT;
break;
case EOT:
/* XXX: EOT shouldn't be an instoption, I don't think */
GEN(&$$)->bits3.generic.end_of_thread = 1;
break;
}
} }
| /* empty, header defaults to zeroes. */ | /* empty, header defaults to zeroes. */
{ {