mirror of
https://github.com/tiagovignatti/intel-gpu-tools.git
synced 2025-11-04 03:58:27 +00:00
assembler/bdw: Add the start of a gen8 disassembler
Directly taken from Mesa. v2 (Ben): Updated copyright Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
This commit is contained in:
Damien Lespiau
Ben Widawsky
parent
42d8d57c8c
commit
bc3bf098a9
@ -18,6 +18,7 @@ libbrw_la_SOURCES = \
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brw_eu_util.c \
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brw_reg.h \
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brw_structs.h \
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gen8_disasm.c \
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gen8_instruction.h \
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gen8_instruction.c \
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ralloc.c \
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@ -28,6 +28,7 @@
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#include "gen4asm.h"
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#include "brw_eu.h"
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#include "gen8_instruction.h"
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static const struct option longopts[] = {
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{ NULL, 0, NULL, 0 }
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@ -99,7 +100,7 @@ static void usage(void)
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fprintf(stderr, "usage: intel-gen4disasm [options] inputfile\n");
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fprintf(stderr, "\t-b, --binary C style binary output\n");
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fprintf(stderr, "\t-o, --output {outputfile} Specify output file\n");
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fprintf(stderr, "\t-g, --gen <4|5|6|7> Specify GPU generation\n");
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fprintf(stderr, "\t-g, --gen <4|5|6|7|8> Specify GPU generation\n");
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}
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int main(int argc, char **argv)
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@ -126,7 +127,7 @@ int main(int argc, char **argv)
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case 'g':
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gen = strtol(optarg, NULL, 10);
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if (gen < 4 || gen > 7) {
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if (gen < 4 || gen > 8) {
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usage();
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exit(1);
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}
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@ -167,6 +168,10 @@ int main(int argc, char **argv)
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}
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for (inst = program->first; inst; inst = inst->next)
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if (gen >= 8)
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gen8_disassemble(output, &inst->insn.gen8, gen);
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else
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brw_disasm (output, &inst->insn.gen, gen);
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exit (0);
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}
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993
assembler/gen8_disasm.c
Normal file
993
assembler/gen8_disasm.c
Normal file
@ -0,0 +1,993 @@
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/*
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* Copyright © 2013 Intel Corporation
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*
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* Permission to use, copy, modify, distribute, and sell this software and its
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* documentation for any purpose is hereby granted without fee, provided that
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* the above copyright notice appear in all copies and that both that copyright
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* notice and this permission notice appear in supporting documentation, and
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* that the name of the copyright holders not be used in advertising or
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* publicity pertaining to distribution of the software without specific,
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* written prior permission. The copyright holders make no representations
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* about the suitability of this software for any purpose. It is provided "as
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* is" without express or implied warranty.
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*
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* THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
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* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
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* EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
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* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
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* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
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* OF THIS SOFTWARE.
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <getopt.h>
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#include <unistd.h>
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#include <stdarg.h>
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#include "brw_context.h"
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#include "brw_defines.h"
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#include "gen8_instruction.h"
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static const struct opcode_desc *m_opcode = opcode_descs;
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static const char *const m_conditional_modifier[16] = {
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/* [0 - BRW_CONDITIONAL_NONE] */ "",
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/* [1 - BRW_CONDITIONAL_Z] */ ".e",
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/* [2 - BRW_CONDITIONAL_NZ] */ ".ne",
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/* [3 - BRW_CONDITIONAL_G] */ ".g",
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/* [4 - BRW_CONDITIONAL_GE] */ ".ge",
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/* [5 - BRW_CONDITIONAL_L] */ ".l",
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/* [6 - BRW_CONDITIONAL_LE] */ ".le",
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/* [7 - Reserved] */ NULL,
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/* [8 - BRW_CONDITIONAL_O] */ ".o",
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/* [9 - BRW_CONDITIONAL_U] */ ".u",
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/* [a-f - Reserved] */
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};
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static const char *const m_negate[2] = { "", "-" };
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static const char *const m_abs[2] = { "", "(abs)" };
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static const char *const m_vert_stride[16] = {
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"0",
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"1",
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"2",
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"4",
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"8",
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"16",
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"32",
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};
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static const char *const width[8] = {
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"1",
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"2",
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"4",
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"8",
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"16",
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};
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static const char *const m_horiz_stride[4] = {
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"0",
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"1",
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"2",
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"4"
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};
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static const char *const m_chan_sel[4] = { "x", "y", "z", "w" };
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static const char *const m_debug_ctrl[2] = { "", ".breakpoint" };
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static const char *const m_saturate[2] = { "", ".sat" };
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static const char *const m_accwr[2] = { "", "AccWrEnable" };
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static const char *const m_maskctrl[2] = { "WE_normal", "WE_all" };
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static const char *const m_exec_size[8] = {
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"1",
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"2",
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"4",
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"8",
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"16",
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"32",
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};
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static const char *const m_pred_inv[2] = { "+", "-" };
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static const char *const m_pred_ctrl_align16[16] = {
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"",
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"",
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".x",
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".y",
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".z",
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".w",
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".any4h",
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".all4h",
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};
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static const char *const m_pred_ctrl_align1[16] = {
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"",
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"",
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".anyv",
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".allv",
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".any2h",
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".all2h",
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".any4h",
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".all4h",
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".any8h",
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".all8h",
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".any16h",
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".all16h",
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".any32h",
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".all32h",
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};
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static const char *const m_thread_ctrl[4] = {
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"",
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"atomic",
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"switch",
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};
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static const char *const m_dep_ctrl[4] = {
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"",
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"NoDDClr",
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"NoDDChk",
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"NoDDClr,NoDDChk",
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};
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static const char *const m_mask_ctrl[4] = {
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"",
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"nomask",
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};
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static const char *const m_access_mode[2] = { "align1", "align16" };
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static const char *const m_reg_type[8] = {
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"UD",
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"D",
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"UW",
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"W",
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"UB",
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"B",
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"DF",
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"F",
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};
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static const int reg_type_size[8] = {
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/* UD */ 4,
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/* D */ 4,
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/* UW */ 2,
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/* W */ 2,
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/* UB */ 1,
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/* B */ 1,
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/* DF */ 8,
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/* F */ 4,
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};
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static const char *const m_reg_file[4] = {
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"A",
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"g",
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NULL,
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"imm",
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};
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static const char *const m_writemask[16] = {
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".(none)",
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".x",
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".y",
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".xy",
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".z",
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".xz",
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".yz",
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".xyz",
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".w",
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".xw",
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".yw",
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".xyw",
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".zw",
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".xzw",
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".yzw",
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"",
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};
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static const char *const m_eot[2] = { "", "EOT" };
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static const char *const m_sfid[16] = {
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/* [0 - BRW_SFID_NULL] */ "null",
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/* [1 - Reserved] */ NULL,
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/* [2 - BRW_SFID_SAMPLER] */ "sampler",
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/* [3 - BRW_SFID_MESSAGE_GATEWAY] */ "gateway",
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/* [4 - GEN6_SFID_DATAPORT_SAMPLER_CACHE] */ "dp/sampler_cache",
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/* [5 - GEN6_SFID_DATAPORT_RENDER_CACHE] */ "dp/render_cache",
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/* [6 - BRW_SFID_URB] */ "URB",
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/* [7 - BRW_SFID_THREAD_SPAWNER] */ "thread_spawner",
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/* [8 - BRW_SFID_VME] */ "vme",
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/* [9 - GEN6_SFID_DATAPORT_CONSTANT_CACHE] */ "dp/constant_cache",
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/* [a - GEN7_SFID_DATAPORT_DATA_CACHE] */ "dp/data_cache",
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/* [b - GEN7_SFID_PI] */ "pi",
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/* [c - HSW_SFID_DATAPORT_DATA_CACHE_1] */ "dp/data_cache:1",
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/* [d - HSW_SFID_CRE] */ "cre",
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/* [e-f - Reserved */ NULL, NULL,
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};
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#if 0
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static const char *const dp_rc_msg_type[16] = {
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[BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ] = "OWORD block read",
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[GEN6_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ] = "RT UNORM read",
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[GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ] = "OWORD dual block read",
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[GEN6_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ] = "media block read",
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[GEN6_DATAPORT_READ_MESSAGE_OWORD_UNALIGN_BLOCK_READ] = "OWORD unaligned block read",
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[GEN6_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ] = "DWORD scattered read",
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[GEN6_DATAPORT_WRITE_MESSAGE_DWORD_ATOMIC_WRITE] = "DWORD atomic write",
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[GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE] = "OWORD block write",
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[GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE] = "OWORD dual block write",
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[GEN6_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE] = "media block write",
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[GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE] = "DWORD scattered write",
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[GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE] = "RT write",
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[GEN6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE] = "streamed VB write",
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[GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE] = "RT UNORMc write",
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};
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#endif
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static const char *const m_math_function[16] = {
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/* [0 - Reserved] */ NULL,
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/* [1 - BRW_MATH_FUNCTION_INV] */ "inv",
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/* [2 - BRW_MATH_FUNCTION_LOG] */ "log",
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/* [3 - BRW_MATH_FUNCTION_EXP] */ "exp",
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/* [4 - BRW_MATH_FUNCTION_SQRT] */ "sqrt",
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/* [5 - BRW_MATH_FUNCTION_RSQ] */ "rsq",
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/* [6 - BRW_MATH_FUNCTION_SIN] */ "sin",
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/* [7 - BRW_MATH_FUNCTION_COS] */ "cos",
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/* [8 - Reserved] */ NULL,
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/* [9 - BRW_MATH_FUNCTION_FDIV] */ "fdiv",
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/* [a - BRW_MATH_FUNCTION_POW] */ "pow",
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/* [b - BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER] */ "intdivmod",
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/* [c - BRW_MATH_FUNCTION_INT_DIV_QUOTIENT] */ "intdiv",
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/* [d - BRW_MATH_FUNCTION_INT_DIV_REMAINDER] */ "intmod",
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/* [e - GEN8_MATH_FUNCTION_INVM] */ "invm",
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/* [f - GEN8_MATH_FUNCTION_RSQRTM] */ "rsqrtm",
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};
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static const char *const m_urb_opcode[16] = {
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/* [0] */ "write HWord",
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/* [1] */ "write OWord",
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/* [2] */ "read HWord",
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/* [3] */ "read OWord",
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/* [4] */ "atomic mov",
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/* [5] */ "atomic inc",
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/* [6] */ "atomic add",
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/* [7] */ "SIMD8 write",
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/* [8] */ "SIMD8 read",
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/* [9-15] - reserved */
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};
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static const char *const m_urb_interleave[2] = { "", "interleaved" };
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static int column;
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static int
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string(FILE *file, const char *string)
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{
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fputs(string, file);
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column += strlen(string);
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return 0;
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}
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static int
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format(FILE *f, const char *format, ...)
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{
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char buf[1024];
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va_list args;
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va_start(args, format);
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vsnprintf(buf, sizeof(buf) - 1, format, args);
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va_end(args);
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string(f, buf);
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return 0;
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}
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static int
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newline(FILE *f)
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{
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putc('\n', f);
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column = 0;
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return 0;
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}
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static int
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pad(FILE *f, int c)
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{
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do
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string(f, " ");
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while (column < c);
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return 0;
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}
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static int
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control(FILE *file, const char *name, const char *const ctrl[],
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unsigned id, int *space)
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{
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if (!ctrl[id]) {
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fprintf(file, "*** invalid %s value %d ", name, id);
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return 1;
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}
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if (ctrl[id][0])
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{
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if (space && *space)
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string(file, " ");
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string(file, ctrl[id]);
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if (space)
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*space = 1;
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}
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return 0;
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}
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static int
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print_opcode(FILE *file, int id)
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{
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if (!m_opcode[id].name) {
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format(file, "*** invalid opcode value %d ", id);
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return 1;
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}
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string(file, m_opcode[id].name);
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return 0;
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}
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static int
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reg(FILE *file, unsigned reg_file, unsigned _reg_nr)
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{
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int err = 0;
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if (reg_file == BRW_ARCHITECTURE_REGISTER_FILE) {
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switch (_reg_nr & 0xf0) {
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case BRW_ARF_NULL:
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string(file, "null");
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return -1;
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case BRW_ARF_ADDRESS:
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format(file, "a%d", _reg_nr & 0x0f);
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break;
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case BRW_ARF_ACCUMULATOR:
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format(file, "acc%d", _reg_nr & 0x0f);
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break;
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case BRW_ARF_FLAG:
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format(file, "f%d", _reg_nr & 0x0f);
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break;
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case BRW_ARF_MASK:
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format(file, "mask%d", _reg_nr & 0x0f);
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break;
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case BRW_ARF_MASK_STACK:
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format(file, "msd%d", _reg_nr & 0x0f);
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break;
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case BRW_ARF_STATE:
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format(file, "sr%d", _reg_nr & 0x0f);
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break;
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case BRW_ARF_CONTROL:
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format(file, "cr%d", _reg_nr & 0x0f);
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break;
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case BRW_ARF_NOTIFICATION_COUNT:
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format(file, "n%d", _reg_nr & 0x0f);
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break;
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case BRW_ARF_IP:
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string(file, "ip");
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return -1;
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break;
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default:
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format(file, "ARF%d", _reg_nr);
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break;
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}
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} else {
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err |= control(file, "src reg file", m_reg_file, reg_file, NULL);
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format(file, "%d", _reg_nr);
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}
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return err;
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}
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static int
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dest(FILE *file, struct gen8_instruction *inst)
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{
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int err = 0;
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if (gen8_access_mode(inst) == BRW_ALIGN_1)
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{
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assert(gen8_dst_address_mode(inst) == BRW_ADDRESS_DIRECT);
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err |= reg(file, gen8_dst_reg_file(inst), gen8_dst_da_reg_nr(inst));
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if (err == -1)
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return 0;
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if (gen8_dst_da1_subreg_nr(inst))
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format(file, ".%d", gen8_dst_da1_subreg_nr(inst) /
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reg_type_size[gen8_dst_reg_type(inst)]);
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string(file, "<");
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err |= control(file, "horiz stride", m_horiz_stride, gen8_dst_da1_hstride(inst), NULL);
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string(file, ">");
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err |= control(file, "dest reg encoding", m_reg_type, gen8_dst_reg_type(inst), NULL);
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}
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else
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{
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assert(gen8_dst_address_mode(inst) == BRW_ADDRESS_DIRECT);
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err |= reg(file, gen8_dst_reg_file(inst), gen8_dst_da_reg_nr(inst));
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if (err == -1)
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return 0;
|
||||
if (gen8_dst_da16_subreg_nr(inst))
|
||||
format(file, ".%d", gen8_dst_da16_subreg_nr(inst) /
|
||||
reg_type_size[gen8_dst_reg_type(inst)]);
|
||||
string(file, "<1>");
|
||||
err |= control(file, "writemask", m_writemask, gen8_da16_writemask(inst), NULL);
|
||||
err |= control(file, "dest reg encoding", m_reg_type, gen8_dst_reg_type(inst), NULL);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if 0
|
||||
static int
|
||||
dest_3src(FILE *file, gen8_instruction *inst)
|
||||
{
|
||||
int err = 0;
|
||||
uint32_t reg_file;
|
||||
|
||||
if (inst->bits1.da3src.dest_reg_file)
|
||||
reg_file = BRW_MESSAGE_REGISTER_FILE;
|
||||
else
|
||||
reg_file = BRW_GENERAL_REGISTER_FILE;
|
||||
|
||||
err |= reg(file, reg_file, inst->bits1.da3src.dest_reg_nr);
|
||||
if (err == -1)
|
||||
return 0;
|
||||
if (inst->bits1.da3src.dest_subreg_nr)
|
||||
format(file, ".%d", inst->bits1.da3src.dest_subreg_nr);
|
||||
string(file, "<1>");
|
||||
err |= control(file, "writemask", m_writemask, inst->bits1.da3src.dest_writemask, NULL);
|
||||
err |= control(file, "dest reg encoding", m_reg_type, BRW_REGISTER_TYPE_F, NULL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static int
|
||||
src_align1_region(FILE *file, unsigned vert_stride, unsigned _width,
|
||||
unsigned horiz_stride)
|
||||
{
|
||||
int err = 0;
|
||||
string(file, "<");
|
||||
err |= control(file, "vert stride", m_vert_stride, vert_stride, NULL);
|
||||
string(file, ",");
|
||||
err |= control(file, "width", width, _width, NULL);
|
||||
string(file, ",");
|
||||
err |= control(file, "horiz_stride", m_horiz_stride, horiz_stride, NULL);
|
||||
string(file, ">");
|
||||
return err;
|
||||
}
|
||||
|
||||
static int
|
||||
src_da1(FILE *file, unsigned type, unsigned reg_file,
|
||||
unsigned vert_stride, unsigned _width, unsigned horiz_stride,
|
||||
unsigned reg_num, unsigned sub_reg_num, unsigned _abs, unsigned negate)
|
||||
{
|
||||
int err = 0;
|
||||
err |= control(file, "negate", m_negate, negate, NULL);
|
||||
err |= control(file, "abs", m_abs, _abs, NULL);
|
||||
|
||||
err |= reg(file, reg_file, reg_num);
|
||||
if (err == -1)
|
||||
return 0;
|
||||
if (sub_reg_num)
|
||||
format(file, ".%d", sub_reg_num / reg_type_size[type]); /* use formal style like spec */
|
||||
src_align1_region(file, vert_stride, _width, horiz_stride);
|
||||
err |= control(file, "src reg encoding", m_reg_type, type, NULL);
|
||||
return err;
|
||||
}
|
||||
|
||||
static int
|
||||
src_da16(FILE *file,
|
||||
unsigned _reg_type,
|
||||
unsigned reg_file,
|
||||
unsigned vert_stride,
|
||||
unsigned _reg_nr,
|
||||
unsigned _subreg_nr,
|
||||
unsigned _abs,
|
||||
unsigned negate,
|
||||
unsigned swz_x,
|
||||
unsigned swz_y,
|
||||
unsigned swz_z,
|
||||
unsigned swz_w)
|
||||
{
|
||||
int err = 0;
|
||||
err |= control(file, "negate", m_negate, negate, NULL);
|
||||
err |= control(file, "abs", m_abs, _abs, NULL);
|
||||
|
||||
err |= reg(file, reg_file, _reg_nr);
|
||||
if (err == -1)
|
||||
return 0;
|
||||
if (_subreg_nr)
|
||||
/* bit4 for subreg number byte addressing. Make this same meaning as
|
||||
in da1 case, so output looks consistent. */
|
||||
format(file, ".%d", 16 / reg_type_size[_reg_type]);
|
||||
string(file, "<");
|
||||
err |= control(file, "vert stride", m_vert_stride, vert_stride, NULL);
|
||||
string(file, ",4,1>");
|
||||
/*
|
||||
* Three kinds of swizzle display:
|
||||
* identity - nothing printed
|
||||
* 1->all - print the single channel
|
||||
* 1->1 - print the mapping
|
||||
*/
|
||||
if (swz_x == BRW_CHANNEL_X &&
|
||||
swz_y == BRW_CHANNEL_Y &&
|
||||
swz_z == BRW_CHANNEL_Z &&
|
||||
swz_w == BRW_CHANNEL_W)
|
||||
{
|
||||
;
|
||||
}
|
||||
else if (swz_x == swz_y && swz_x == swz_z && swz_x == swz_w)
|
||||
{
|
||||
string(file, ".");
|
||||
err |= control(file, "channel select", m_chan_sel, swz_x, NULL);
|
||||
}
|
||||
else
|
||||
{
|
||||
string(file, ".");
|
||||
err |= control(file, "channel select", m_chan_sel, swz_x, NULL);
|
||||
err |= control(file, "channel select", m_chan_sel, swz_y, NULL);
|
||||
err |= control(file, "channel select", m_chan_sel, swz_z, NULL);
|
||||
err |= control(file, "channel select", m_chan_sel, swz_w, NULL);
|
||||
}
|
||||
err |= control(file, "src da16 reg type", m_reg_type, _reg_type, NULL);
|
||||
return err;
|
||||
}
|
||||
|
||||
#if 0
|
||||
static int
|
||||
src0_3src(FILE *file, gen8_instruction *inst)
|
||||
{
|
||||
int err = 0;
|
||||
unsigned swz_x = (inst->bits2.da3src.src0_swizzle >> 0) & 0x3;
|
||||
unsigned swz_y = (inst->bits2.da3src.src0_swizzle >> 2) & 0x3;
|
||||
unsigned swz_z = (inst->bits2.da3src.src0_swizzle >> 4) & 0x3;
|
||||
unsigned swz_w = (inst->bits2.da3src.src0_swizzle >> 6) & 0x3;
|
||||
|
||||
err |= control(file, "negate", m_negate, inst->bits1.da3src.src0_negate, NULL);
|
||||
err |= control(file, "abs", m_abs, inst->bits1.da3src.src0_abs, NULL);
|
||||
|
||||
err |= reg(file, BRW_GENERAL_REGISTER_FILE, inst->bits2.da3src.src0_reg_nr);
|
||||
if (err == -1)
|
||||
return 0;
|
||||
if (inst->bits2.da3src.src0_subreg_nr)
|
||||
format(file, ".%d", inst->bits2.da3src.src0_subreg_nr);
|
||||
string(file, "<4,1,1>");
|
||||
err |= control(file, "src da16 reg type", m_reg_type,
|
||||
BRW_REGISTER_TYPE_F, NULL);
|
||||
/*
|
||||
* Three kinds of swizzle display:
|
||||
* identity - nothing printed
|
||||
* 1->all - print the single channel
|
||||
* 1->1 - print the mapping
|
||||
*/
|
||||
if (swz_x == BRW_CHANNEL_X &&
|
||||
swz_y == BRW_CHANNEL_Y &&
|
||||
swz_z == BRW_CHANNEL_Z &&
|
||||
swz_w == BRW_CHANNEL_W)
|
||||
{
|
||||
;
|
||||
}
|
||||
else if (swz_x == swz_y && swz_x == swz_z && swz_x == swz_w)
|
||||
{
|
||||
string(file, ".");
|
||||
err |= control(file, "channel select", m_chan_sel, swz_x, NULL);
|
||||
}
|
||||
else
|
||||
{
|
||||
string(file, ".");
|
||||
err |= control(file, "channel select", m_chan_sel, swz_x, NULL);
|
||||
err |= control(file, "channel select", m_chan_sel, swz_y, NULL);
|
||||
err |= control(file, "channel select", m_chan_sel, swz_z, NULL);
|
||||
err |= control(file, "channel select", m_chan_sel, swz_w, NULL);
|
||||
}
|
||||
return err;
|
||||
}
|
||||
|
||||
static int
|
||||
src1_3src(FILE *file, gen8_instruction *inst)
|
||||
{
|
||||
int err = 0;
|
||||
unsigned swz_x = (inst->bits2.da3src.src1_swizzle >> 0) & 0x3;
|
||||
unsigned swz_y = (inst->bits2.da3src.src1_swizzle >> 2) & 0x3;
|
||||
unsigned swz_z = (inst->bits2.da3src.src1_swizzle >> 4) & 0x3;
|
||||
unsigned swz_w = (inst->bits2.da3src.src1_swizzle >> 6) & 0x3;
|
||||
unsigned src1_subreg_nr = (inst->bits2.da3src.src1_subreg_nr_low |
|
||||
(inst->bits3.da3src.src1_subreg_nr_high << 2));
|
||||
|
||||
err |= control(file, "negate", m_negate, inst->bits1.da3src.src1_negate,
|
||||
NULL);
|
||||
err |= control(file, "abs", m_abs, inst->bits1.da3src.src1_abs, NULL);
|
||||
|
||||
err |= reg(file, BRW_GENERAL_REGISTER_FILE,
|
||||
inst->bits3.da3src.src1_reg_nr);
|
||||
if (err == -1)
|
||||
return 0;
|
||||
if (src1_subreg_nr)
|
||||
format(file, ".%d", src1_subreg_nr);
|
||||
string(file, "<4,1,1>");
|
||||
err |= control(file, "src da16 reg type", m_reg_type,
|
||||
BRW_REGISTER_TYPE_F, NULL);
|
||||
/*
|
||||
* Three kinds of swizzle display:
|
||||
* identity - nothing printed
|
||||
* 1->all - print the single channel
|
||||
* 1->1 - print the mapping
|
||||
*/
|
||||
if (swz_x == BRW_CHANNEL_X &&
|
||||
swz_y == BRW_CHANNEL_Y &&
|
||||
swz_z == BRW_CHANNEL_Z &&
|
||||
swz_w == BRW_CHANNEL_W)
|
||||
{
|
||||
;
|
||||
}
|
||||
else if (swz_x == swz_y && swz_x == swz_z && swz_x == swz_w)
|
||||
{
|
||||
string(file, ".");
|
||||
err |= control(file, "channel select", m_chan_sel, swz_x, NULL);
|
||||
}
|
||||
else
|
||||
{
|
||||
string(file, ".");
|
||||
err |= control(file, "channel select", m_chan_sel, swz_x, NULL);
|
||||
err |= control(file, "channel select", m_chan_sel, swz_y, NULL);
|
||||
err |= control(file, "channel select", m_chan_sel, swz_z, NULL);
|
||||
err |= control(file, "channel select", m_chan_sel, swz_w, NULL);
|
||||
}
|
||||
return err;
|
||||
}
|
||||
|
||||
|
||||
static int
|
||||
src2_3src(FILE *file, gen8_instruction *inst)
|
||||
{
|
||||
int err = 0;
|
||||
unsigned swz_x = (inst->bits3.da3src.src2_swizzle >> 0) & 0x3;
|
||||
unsigned swz_y = (inst->bits3.da3src.src2_swizzle >> 2) & 0x3;
|
||||
unsigned swz_z = (inst->bits3.da3src.src2_swizzle >> 4) & 0x3;
|
||||
unsigned swz_w = (inst->bits3.da3src.src2_swizzle >> 6) & 0x3;
|
||||
|
||||
err |= control(file, "negate", m_negate, inst->bits1.da3src.src2_negate,
|
||||
NULL);
|
||||
err |= control(file, "abs", m_abs, inst->bits1.da3src.src2_abs, NULL);
|
||||
|
||||
err |= reg(file, BRW_GENERAL_REGISTER_FILE,
|
||||
inst->bits3.da3src.src2_reg_nr);
|
||||
if (err == -1)
|
||||
return 0;
|
||||
if (inst->bits3.da3src.src2_subreg_nr)
|
||||
format(file, ".%d", inst->bits3.da3src.src2_subreg_nr);
|
||||
string(file, "<4,1,1>");
|
||||
err |= control(file, "src da16 reg type", m_reg_type,
|
||||
BRW_REGISTER_TYPE_F, NULL);
|
||||
/*
|
||||
* Three kinds of swizzle display:
|
||||
* identity - nothing printed
|
||||
* 1->all - print the single channel
|
||||
* 1->1 - print the mapping
|
||||
*/
|
||||
if (swz_x == BRW_CHANNEL_X &&
|
||||
swz_y == BRW_CHANNEL_Y &&
|
||||
swz_z == BRW_CHANNEL_Z &&
|
||||
swz_w == BRW_CHANNEL_W)
|
||||
{
|
||||
;
|
||||
}
|
||||
else if (swz_x == swz_y && swz_x == swz_z && swz_x == swz_w)
|
||||
{
|
||||
string(file, ".");
|
||||
err |= control(file, "channel select", m_chan_sel, swz_x, NULL);
|
||||
}
|
||||
else
|
||||
{
|
||||
string(file, ".");
|
||||
err |= control(file, "channel select", m_chan_sel, swz_x, NULL);
|
||||
err |= control(file, "channel select", m_chan_sel, swz_y, NULL);
|
||||
err |= control(file, "channel select", m_chan_sel, swz_z, NULL);
|
||||
err |= control(file, "channel select", m_chan_sel, swz_w, NULL);
|
||||
}
|
||||
return err;
|
||||
}
|
||||
#endif
|
||||
|
||||
static int
|
||||
imm(FILE *file, unsigned type, struct gen8_instruction *inst)
|
||||
{
|
||||
switch (type) {
|
||||
case BRW_REGISTER_TYPE_UD:
|
||||
format(file, "0x%08xUD", gen8_src1_imm_ud(inst));
|
||||
break;
|
||||
case BRW_REGISTER_TYPE_D:
|
||||
format(file, "%dD", (int) gen8_src1_imm_d(inst));
|
||||
break;
|
||||
case BRW_REGISTER_TYPE_UW:
|
||||
format(file, "0x%04xUW", (uint16_t) gen8_src1_imm_ud(inst));
|
||||
break;
|
||||
case BRW_REGISTER_TYPE_W:
|
||||
format(file, "%dW", (int16_t) gen8_src1_imm_d(inst));
|
||||
break;
|
||||
case BRW_REGISTER_TYPE_UB:
|
||||
format(file, "0x%02xUB", (int8_t) gen8_src1_imm_ud(inst));
|
||||
break;
|
||||
case BRW_REGISTER_TYPE_VF:
|
||||
format(file, "Vector Float");
|
||||
break;
|
||||
case BRW_REGISTER_TYPE_V:
|
||||
format(file, "0x%08xV", gen8_src1_imm_ud(inst));
|
||||
break;
|
||||
case BRW_REGISTER_TYPE_F:
|
||||
format(file, "%-gF", gen8_src1_imm_f(inst));
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
src0(FILE *file, struct gen8_instruction *inst)
|
||||
{
|
||||
if (gen8_src0_reg_file(inst) == BRW_IMMEDIATE_VALUE)
|
||||
return imm(file, gen8_src0_reg_type(inst), inst);
|
||||
|
||||
if (gen8_access_mode(inst) == BRW_ALIGN_1)
|
||||
{
|
||||
assert(gen8_src0_address_mode(inst) == BRW_ADDRESS_DIRECT);
|
||||
return src_da1(file,
|
||||
gen8_src0_reg_type(inst),
|
||||
gen8_src0_reg_file(inst),
|
||||
gen8_src0_vert_stride(inst),
|
||||
gen8_src0_da1_width(inst),
|
||||
gen8_src0_da1_hstride(inst),
|
||||
gen8_src0_da_reg_nr(inst),
|
||||
gen8_src0_da1_subreg_nr(inst),
|
||||
gen8_src0_abs(inst),
|
||||
gen8_src0_negate(inst));
|
||||
}
|
||||
else
|
||||
{
|
||||
assert(gen8_src0_address_mode(inst) == BRW_ADDRESS_DIRECT);
|
||||
return src_da16(file,
|
||||
gen8_src0_reg_type(inst),
|
||||
gen8_src0_reg_file(inst),
|
||||
gen8_src0_vert_stride(inst),
|
||||
gen8_src0_da_reg_nr(inst),
|
||||
gen8_src0_da16_subreg_nr(inst),
|
||||
gen8_src0_abs(inst),
|
||||
gen8_src0_negate(inst),
|
||||
gen8_src0_da16_swiz_x(inst),
|
||||
gen8_src0_da16_swiz_y(inst),
|
||||
gen8_src0_da16_swiz_z(inst),
|
||||
gen8_src0_da16_swiz_w(inst));
|
||||
}
|
||||
}
|
||||
|
||||
static int
|
||||
src1(FILE *file, struct gen8_instruction *inst)
|
||||
{
|
||||
if (gen8_src1_reg_file(inst) == BRW_IMMEDIATE_VALUE)
|
||||
return imm(file, gen8_src1_reg_type(inst), inst);
|
||||
|
||||
if (gen8_access_mode(inst) == BRW_ALIGN_1)
|
||||
{
|
||||
assert(gen8_src1_address_mode(inst) == BRW_ADDRESS_DIRECT);
|
||||
return src_da1(file,
|
||||
gen8_src1_reg_type(inst),
|
||||
gen8_src1_reg_file(inst),
|
||||
gen8_src1_vert_stride(inst),
|
||||
gen8_src1_da1_width(inst),
|
||||
gen8_src1_da1_hstride(inst),
|
||||
gen8_src1_da_reg_nr(inst),
|
||||
gen8_src1_da1_subreg_nr(inst),
|
||||
gen8_src1_abs(inst),
|
||||
gen8_src1_negate(inst));
|
||||
}
|
||||
else
|
||||
{
|
||||
assert(gen8_src1_address_mode(inst) == BRW_ADDRESS_DIRECT);
|
||||
return src_da16(file,
|
||||
gen8_src1_reg_type(inst),
|
||||
gen8_src1_reg_file(inst),
|
||||
gen8_src1_vert_stride(inst),
|
||||
gen8_src1_da_reg_nr(inst),
|
||||
gen8_src1_da16_subreg_nr(inst),
|
||||
gen8_src1_abs(inst),
|
||||
gen8_src1_negate(inst),
|
||||
gen8_src1_da16_swiz_x(inst),
|
||||
gen8_src1_da16_swiz_y(inst),
|
||||
gen8_src1_da16_swiz_z(inst),
|
||||
gen8_src1_da16_swiz_w(inst));
|
||||
}
|
||||
}
|
||||
|
||||
static int esize[6] = { 1, 2, 4, 8, 16, 32 };
|
||||
|
||||
static int
|
||||
qtr_ctrl(FILE *file, struct gen8_instruction *inst)
|
||||
{
|
||||
int qtr_ctl = gen8_qtr_control(inst);
|
||||
int exec_size = esize[gen8_exec_size(inst)];
|
||||
|
||||
if (exec_size == 8) {
|
||||
switch (qtr_ctl) {
|
||||
case 0:
|
||||
string(file, " 1Q");
|
||||
break;
|
||||
case 1:
|
||||
string(file, " 2Q");
|
||||
break;
|
||||
case 2:
|
||||
string(file, " 3Q");
|
||||
break;
|
||||
case 3:
|
||||
string(file, " 4Q");
|
||||
break;
|
||||
}
|
||||
} else if (exec_size == 16) {
|
||||
if (qtr_ctl < 2)
|
||||
string(file, " 1H");
|
||||
else
|
||||
string(file, " 2H");
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
gen8_disassemble(FILE *file, struct gen8_instruction *insn, int gen)
|
||||
{
|
||||
int err = 0;
|
||||
int space = 0;
|
||||
|
||||
const int opcode = gen8_opcode(insn);
|
||||
|
||||
if (gen8_pred_control(insn)) {
|
||||
string(file, "(");
|
||||
err |= control(file, "predicate inverse", m_pred_inv, gen8_pred_inv(insn), NULL);
|
||||
format(file, "f%d", gen8_flag_reg_nr(insn));
|
||||
if (gen8_flag_subreg_nr(insn))
|
||||
format(file, ".%d", gen8_flag_subreg_nr(insn));
|
||||
if (gen8_access_mode(insn) == BRW_ALIGN_1) {
|
||||
err |= control(file, "predicate control align1", m_pred_ctrl_align1,
|
||||
gen8_pred_control(insn), NULL);
|
||||
} else {
|
||||
err |= control(file, "predicate control align16", m_pred_ctrl_align16,
|
||||
gen8_pred_control(insn), NULL);
|
||||
}
|
||||
string(file, ") ");
|
||||
}
|
||||
|
||||
err |= print_opcode(file, opcode);
|
||||
err |= control(file, "saturate", m_saturate, gen8_saturate(insn), NULL);
|
||||
err |= control(file, "debug control", m_debug_ctrl, gen8_debug_control(insn), NULL);
|
||||
|
||||
if (opcode == BRW_OPCODE_MATH) {
|
||||
string(file, " ");
|
||||
err |= control(file, "function", m_math_function, gen8_math_function(insn),
|
||||
NULL);
|
||||
} else if (opcode != BRW_OPCODE_SEND && opcode != BRW_OPCODE_SENDC) {
|
||||
err |= control(file, "conditional modifier", m_conditional_modifier,
|
||||
gen8_cond_modifier(insn), NULL);
|
||||
|
||||
/* If we're using the conditional modifier, print the flag reg used. */
|
||||
if (gen8_cond_modifier(insn) && opcode != BRW_OPCODE_SEL) {
|
||||
format(file, ".f%d", gen8_flag_reg_nr(insn));
|
||||
if (gen8_flag_subreg_nr(insn))
|
||||
format(file, ".%d", gen8_flag_subreg_nr(insn));
|
||||
}
|
||||
}
|
||||
|
||||
if (opcode != BRW_OPCODE_NOP) {
|
||||
string(file, "(");
|
||||
err |= control(file, "execution size", m_exec_size, gen8_exec_size(insn), NULL);
|
||||
string(file, ")");
|
||||
}
|
||||
|
||||
if (m_opcode[opcode].nsrc == 3) {
|
||||
string(file, "XXX: 3-src");
|
||||
#if 0
|
||||
pad(file, 16);
|
||||
err |= dest_3src(file, this);
|
||||
|
||||
pad(file, 32);
|
||||
err |= src0_3src(file, this);
|
||||
|
||||
pad(file, 48);
|
||||
err |= src1_3src(file, this);
|
||||
|
||||
pad(file, 64);
|
||||
err |= src2_3src(file, this);
|
||||
#endif
|
||||
} else {
|
||||
if (m_opcode[opcode].ndst > 0) {
|
||||
pad(file, 16);
|
||||
err |= dest(file, insn);
|
||||
} else if (opcode == BRW_OPCODE_ENDIF) {
|
||||
format(file, " %d", gen8_jip(insn));
|
||||
} else if (opcode == BRW_OPCODE_IF ||
|
||||
opcode == BRW_OPCODE_ELSE ||
|
||||
opcode == BRW_OPCODE_WHILE ||
|
||||
opcode == BRW_OPCODE_BREAK ||
|
||||
opcode == BRW_OPCODE_CONTINUE ||
|
||||
opcode == BRW_OPCODE_HALT) {
|
||||
format(file, " %d %d", gen8_jip(insn), gen8_uip(insn));
|
||||
}
|
||||
|
||||
if (m_opcode[opcode].nsrc > 0) {
|
||||
pad(file, 32);
|
||||
err |= src0(file, insn);
|
||||
}
|
||||
if (m_opcode[opcode].nsrc > 1) {
|
||||
pad(file, 48);
|
||||
err |= src1(file, insn);
|
||||
}
|
||||
}
|
||||
|
||||
if (opcode == BRW_OPCODE_SEND || opcode == BRW_OPCODE_SENDC) {
|
||||
const int sfid = gen8_sfid(insn);
|
||||
|
||||
newline(file);
|
||||
pad(file, 16);
|
||||
space = 0;
|
||||
|
||||
err |= control(file, "SFID", m_sfid, sfid, &space);
|
||||
|
||||
switch (sfid) {
|
||||
case BRW_SFID_SAMPLER:
|
||||
format(file, " (%d, %d, %d, %d)",
|
||||
gen8_binding_table_index(insn),
|
||||
gen8_sampler(insn),
|
||||
gen8_sampler_msg_type(insn),
|
||||
gen8_sampler_simd_mode(insn));
|
||||
break;
|
||||
|
||||
case BRW_SFID_URB:
|
||||
space = 1;
|
||||
err |= control(file, "urb opcode", m_urb_opcode,
|
||||
gen8_urb_opcode(insn), &space);
|
||||
err |= control(file, "urb interleave", m_urb_interleave,
|
||||
gen8_urb_interleave(insn), &space);
|
||||
format(file, " %d %d",
|
||||
gen8_urb_global_offset(insn), gen8_urb_per_slot_offset(insn));
|
||||
break;
|
||||
|
||||
case GEN6_SFID_DATAPORT_SAMPLER_CACHE:
|
||||
case GEN6_SFID_DATAPORT_RENDER_CACHE:
|
||||
case GEN6_SFID_DATAPORT_CONSTANT_CACHE:
|
||||
case GEN7_SFID_DATAPORT_DATA_CACHE:
|
||||
format(file, " (%d, 0x%x)",
|
||||
gen8_binding_table_index(insn),
|
||||
gen8_function_control(insn));
|
||||
break;
|
||||
|
||||
default:
|
||||
format(file, "unsupported shared function ID (%d)", sfid);
|
||||
break;
|
||||
}
|
||||
if (space)
|
||||
string(file, " ");
|
||||
format(file, "mlen %d", gen8_mlen(insn));
|
||||
format(file, " rlen %d", gen8_rlen(insn));
|
||||
}
|
||||
pad(file, 64);
|
||||
if (opcode != BRW_OPCODE_NOP) {
|
||||
string(file, "{");
|
||||
space = 1;
|
||||
err |= control(file, "access mode", m_access_mode, gen8_access_mode(insn), &space);
|
||||
err |= control(file, "mask control", m_maskctrl, gen8_mask_control(insn), &space);
|
||||
err |= control(file, "dependency control", m_dep_ctrl, gen8_dep_control(insn), &space);
|
||||
|
||||
err |= qtr_ctrl(file, insn);
|
||||
|
||||
err |= control(file, "thread control", m_thread_ctrl, gen8_thread_control(insn), &space);
|
||||
err |= control(file, "acc write control", m_accwr, gen8_acc_wr_control(insn), &space);
|
||||
if (opcode == BRW_OPCODE_SEND || opcode == BRW_OPCODE_SENDC)
|
||||
err |= control(file, "end of thread", m_eot, gen8_eot(insn), &space);
|
||||
if (space)
|
||||
string(file, " ");
|
||||
string(file, "}");
|
||||
}
|
||||
string(file, ";");
|
||||
newline(file);
|
||||
return err;
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user