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quick_dump: Add VLV DPIO registers

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Add the names of all VLV DPIO registers.

v2: Use the third element to signal DPIO registers, and split
    the code changes to a separate patch

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
This commit is contained in:
Ville Syrjälä 2013-06-26 20:57:34 +03:00 committed by Ben Widawsky
parent e87c2536f6
commit b84b9e230c
3 changed files with 55 additions and 1 deletions
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2
tools/quick_dump/Makefile.am
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@ -25,7 +25,7 @@ EXTRA_DIST = \
base_display.txt base_interrupt.txt base_other.txt base_power.txt base_rings.txt \
gen6_other.txt sandybridge \
gen7_other.txt ivybridge \
vlv_display.txt valleyview \
vlv_display.txt vlv_dpio.txt valleyview \
quick_dump.py \
reg_access.py \
chipset.i chipset.py

1
tools/quick_dump/valleyview
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@ -5,3 +5,4 @@ base_other.txt
base_power.txt
base_rings.txt
gen7_other.txt
vlv_dpio.txt

53
tools/quick_dump/vlv_dpio.txt Normal file
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@ -0,0 +1,53 @@
('DPIO_TX3_SWING_CTL4_A', '0x690', 'DPIO')
('DPIO_TX3_SWING_CTL4_B', '0x2a90', 'DPIO')
('DPIO_DIV_A', '0x800c', 'DPIO')
('DPIO_DIV_B', '0x802c', 'DPIO')
('DPIO_REFSFR_A', '0x8014', 'DPIO')
('DPIO_REFSFR_B', '0x8034', 'DPIO')
('DPIO_CORE_CLK_A', '0x801c', 'DPIO')
('DPIO_CORE_CLK_B', '0x803c', 'DPIO')
('DPIO_IREF_CTL_A', '0x8040', 'DPIO')
('DPIO_IREF_CTL_B', '0x8060', 'DPIO')
('DPIO_IREF_BCAST', '0xc044', 'DPIO')
('DPIO_IREF_A', '0x8044', 'DPIO')
('DPIO_IREF_B', '0x8064', 'DPIO')
('DPIO_PLL_CML_A', '0x804c', 'DPIO')
('DPIO_PLL_CML_B', '0x806c', 'DPIO')
('DPIO_LPF_COEFF_A', '0x8048', 'DPIO')
('DPIO_LPF_COEFF_B', '0x8068', 'DPIO')
('DPIO_CALIBRATION', '0x80ac', 'DPIO')
('DPIO_FASTCLK_DISABLE', '0x8100', 'DPIO')
('DPIO_PCS_TX_0', '0x8200', 'DPIO')
('DPIO_PCS_TX_1', '0x8400', 'DPIO')
('DPIO_PCS_CLK_0', '0x8204', 'DPIO')
('DPIO_PCS_CLK_1', '0x8404', 'DPIO')
('DPIO_PCS_CTL_OVR1_A', '0x8224', 'DPIO')
('DPIO_PCS_CTL_OVR1_B', '0x8424', 'DPIO')
('DPIO_PCS_STAGGER0_A', '0x822c', 'DPIO')
('DPIO_PCS_STAGGER0_B', '0x842c', 'DPIO')
('DPIO_PCS_STAGGER1_A', '0x8230', 'DPIO')
('DPIO_PCS_STAGGER1_B', '0x8430', 'DPIO')
('DPIO_PCS_CLOCKBUF0_A', '0x8238', 'DPIO')
('DPIO_PCS_CLOCKBUF0_B', '0x8438', 'DPIO')
('DPIO_PCS_CLOCKBUF8_A', '0x825c', 'DPIO')
('DPIO_PCS_CLOCKBUF8_B', '0x845c', 'DPIO')
('DPIO_TX_SWING_CTL2_A', '0x8288', 'DPIO')
('DPIO_TX_SWING_CTL2_B', '0x8488', 'DPIO')
('DPIO_TX_SWING_CTL3_A', '0x828c', 'DPIO')
('DPIO_TX_SWING_CTL3_B', '0x848c', 'DPIO')
('DPIO_TX_SWING_CTL4_A', '0x8290', 'DPIO')
('DPIO_TX_SWING_CTL4_B', '0x8490', 'DPIO')
('DPIO_TX_OCALINIT_0', '0x8294', 'DPIO')
('DPIO_TX_OCALINIT_1', '0x8494', 'DPIO')
('DPIO_TX_CTL_0', '0x82ac', 'DPIO')
('DPIO_TX_CTL_1', '0x84ac', 'DPIO')
('DPIO_TX_LANE_0', '0x82b8', 'DPIO')
('DPIO_TX_LANE_1', '0x84b8', 'DPIO')
('DPIO_DATA_CHANNEL1', '0x8220', 'DPIO')
('DPIO_DATA_CHANNEL2', '0x8420', 'DPIO')
('DPIO_PORT0_PCS0', '0x0220', 'DPIO')
('DPIO_PORT0_PCS1', '0x0420', 'DPIO')
('DPIO_PORT1_PCS2', '0x2620', 'DPIO')
('DPIO_PORT1_PCS3', '0x2820', 'DPIO')
('DPIO_DATA_CHANNEL1', '0x8220', 'DPIO')
('DPIO_DATA_CHANNEL2', '0x8420', 'DPIO')