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https://github.com/tiagovignatti/intel-gpu-tools.git
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lib: Add MI_LOAD_REGISTER_IMM
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
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@ -2545,6 +2545,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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#define MI_WAIT_FOR_PIPEA_SCAN_LINE_WINDOW (1<<1)
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#define MI_LOAD_SCAN_LINES_INCL (0x12<<23)
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#define MI_LOAD_REGISTER_IMM ((0x22 << 23) | 1)
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/* Flush */
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#define MI_FLUSH (0x04<<23)
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@ -187,7 +187,6 @@ int fd;
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#define MI_ARB_ON_OFF (0x8 << 23)
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#define MI_DISPLAY_FLIP ((0x14 << 23) | 1)
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#define MI_LOAD_REGISTER_IMM ((0x22 << 23) | 1)
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#define GFX_OP_PIPE_CONTROL ((0x3<<29)|(0x3<<27)|(0x2<<24)|2)
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#define PIPE_CONTROL_QW_WRITE (1<<14)
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@ -52,8 +52,6 @@ struct intel_batchbuffer *batch;
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* should fail if the non-secure handling works correctly.
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*/
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#define MI_LOAD_REGISTER_IMM (0x22<<23)
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static int num_rings = 1;
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static void
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@ -67,7 +65,7 @@ mi_lri_loop(void)
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int ring = random() % num_rings + 1;
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BEGIN_BATCH(4, 0);
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OUT_BATCH(MI_LOAD_REGISTER_IMM | 1);
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OUT_BATCH(MI_LOAD_REGISTER_IMM);
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OUT_BATCH(0x203c); /* RENDER RING CTL */
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OUT_BATCH(0); /* try to stop the ring */
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OUT_BATCH(MI_NOOP);
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@ -120,7 +120,6 @@ static void *thread(void *arg)
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return NULL;
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}
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#define MI_LOAD_REGISTER_IMM (0x22<<23)
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#define MI_STORE_REGISTER_MEM (0x24<<23)
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igt_simple_main
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@ -145,13 +144,13 @@ igt_simple_main
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struct drm_i915_gem_exec_object2 exec[2];
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struct drm_i915_gem_relocation_entry reloc[2];
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uint32_t b[] = {
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MI_LOAD_REGISTER_IMM | 1,
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MI_LOAD_REGISTER_IMM,
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FORCEWAKE_MT,
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2 << 16 | 2,
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MI_STORE_REGISTER_MEM | 1,
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FORCEWAKE_MT,
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0, // to be patched
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MI_LOAD_REGISTER_IMM | 1,
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MI_LOAD_REGISTER_IMM,
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FORCEWAKE_MT,
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2 << 16,
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MI_STORE_REGISTER_MEM | 1,
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