tests: rename gem_tiled_after_untiled_blt into gem_set_tiling_vs_blt

... it checks much more now.

Also update the comments a bit in the testcase.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Daniel Vetter 2012-04-15 23:59:12 +02:00
parent 887e4a58b9
commit b38188ad97
3 changed files with 12 additions and 8 deletions

2
tests/.gitignore vendored
View File

@ -36,12 +36,12 @@ gem_readwrite
gem_reloc_vs_gpu
gem_ringfill
gem_ring_sync_loop
gem_set_tiling_vs_blt
gem_storedw_batches_loop
gem_storedw_loop_blt
gem_storedw_loop_bsd
gem_storedw_loop_render
gem_stress
gem_tiled_after_untiled_blt
gem_tiled_blits
gem_tiled_fence_blits
gem_tiled_partial_pwrite_pread

View File

@ -23,7 +23,7 @@ TESTS_progs = \
gem_mmap_offset_exhaustion \
gem_pwrite \
gem_pread_after_blit \
gem_tiled_after_untiled_blt \
gem_set_tiling_vs_blt \
gem_tiled_pread \
gem_tiled_pread_pwrite \
gem_tiled_partial_pwrite_pread \

View File

@ -25,9 +25,10 @@
*
*/
/** @file gem_tiled_after_untiled_blt.c
/** @file gem_set_tiling_vs_blt.c
*
* Testcase: Check for proper synchronization when switching untiled->tiled
* Testcase: Check for proper synchronization of tiling changes vs. tiled gpu
* access
*
* The blitter on gen3 and earlier needs properly set up fences. Which also
* means that for untiled blits we may not set up a fence before that blt has
@ -38,6 +39,9 @@
* - a blt on an untiled object which is aligned correctly for tiling.
* - a set_tiling to switch that object to tiling
* - another blt without any intervening cpu access that uses this object.
*
* Testcase has been extended to also check tiled->untiled and tiled->tiled
* transitions (i.e. changing stride).
*/
#include <stdlib.h>
@ -111,8 +115,8 @@ static void do_test(uint32_t tiling, unsigned stride,
* tricks */
target_bo = drm_intel_bo_alloc(bufmgr, "target bo", TEST_SIZE, 4096);
/* allocate buffer tiled and touch it, so that it's properly aligned in
* the gtt. */
/* allocate buffer with parameters _after_ transition we want to check
* and touch it, so that it's properly aligned in the gtt. */
test_bo = drm_intel_bo_alloc(bufmgr, "tiled busy bo", TEST_SIZE, 4096);
test_bo_handle = test_bo->handle;
ret = drm_intel_bo_set_tiling(test_bo, &tiling_after, stride_after);
@ -190,8 +194,8 @@ static void do_test(uint32_t tiling, unsigned stride,
ADVANCE_BATCH();
intel_batchbuffer_flush(batch);
/* Now try to trick the kernel the kernel into setting up the fence too
* early. */
/* Now try to trick the kernel the kernel into changing up the fencing
* too early. */
printf("checking .. ");
memset(data, 0, TEST_SIZE);