mirror of
https://github.com/tiagovignatti/intel-gpu-tools.git
synced 2025-06-10 09:26:10 +00:00
Add disassembler (intel-gen4disasm).
Decodes most simple instructions. Still needs work on branching and send.
This commit is contained in:
Keith Packard
Damien Lespiau
parent
082fbe8738
commit
ae85b10cf0
@ -1,7 +1,7 @@
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AM_YFLAGS = -d
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AM_CFLAGS= $(WARN_CFLAGS)
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bin_PROGRAMS = intel-gen4asm
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bin_PROGRAMS = intel-gen4asm intel-gen4disasm
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intel_gen4asm_SOURCES = \
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brw_defines.h \
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@ -11,6 +11,9 @@ intel_gen4asm_SOURCES = \
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lex.l \
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main.c
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intel_gen4disasm_SOURCES = \
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disasm.c disasm-main.c
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gram.h: gram.c
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BUILT_SOURCES = gram.h gram.c lex.c
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@ -523,6 +523,7 @@
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#define BRW_CONDITIONAL_LE 6
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#define BRW_CONDITIONAL_C 7
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#define BRW_CONDITIONAL_O 8
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#define BRW_CONDITIONAL_U 9
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#define BRW_DEBUG_NONE 0
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#define BRW_DEBUG_BREAKPOINT 1
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120
assembler/src/disasm-main.c
Normal file
120
assembler/src/disasm-main.c
Normal file
@ -0,0 +1,120 @@
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/*
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* Copyright © 2008 Keith Packard
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*
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* Permission to use, copy, modify, distribute, and sell this software and its
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* documentation for any purpose is hereby granted without fee, provided that
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* the above copyright notice appear in all copies and that both that copyright
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* notice and this permission notice appear in supporting documentation, and
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* that the name of the copyright holders not be used in advertising or
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* publicity pertaining to distribution of the software without specific,
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* written prior permission. The copyright holders make no representations
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* about the suitability of this software for any purpose. It is provided "as
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* is" without express or implied warranty.
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*
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* THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
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* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
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* EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
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* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
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* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
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* OF THIS SOFTWARE.
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <getopt.h>
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#include <unistd.h>
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#include "gen4asm.h"
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static const struct option longopts[] = {
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{ NULL, 0, NULL, 0 }
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};
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static struct brw_program *
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read_program (FILE *input)
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{
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uint32_t inst[4];
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struct brw_program *program;
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struct brw_program_instruction *entry, **prev;
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int c;
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int n = 0;
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program = malloc (sizeof (struct brw_program));
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program->first = NULL;
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prev = &program->first;
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while ((c = getc (input)) != EOF) {
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if (c == '0') {
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if (fscanf (input, "x%x", &inst[n]) == 1) {
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++n;
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if (n == 4) {
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entry = malloc (sizeof (struct brw_program_instruction));
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memcpy (&entry->instruction, inst, 4 * sizeof (uint32_t));
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entry->next = NULL;
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*prev = entry;
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prev = &entry->next;
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n = 0;
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}
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}
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}
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}
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return program;
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}
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static void usage(void)
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{
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fprintf(stderr, "usage: intel-gen4disasm [-o outputfile] inputfile\n");
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}
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int main(int argc, char **argv)
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{
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struct brw_program *program;
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FILE *input = stdin;
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FILE *output = stdout;
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char *input_filename = NULL;
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char *output_file = NULL;
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int o;
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struct brw_program_instruction *inst;
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while ((o = getopt_long(argc, argv, "o:", longopts, NULL)) != -1) {
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switch (o) {
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case 'o':
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if (strcmp(optarg, "-") != 0)
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output_file = optarg;
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break;
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default:
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usage();
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exit(1);
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}
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}
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argc -= optind;
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argv += optind;
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if (argc != 1) {
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usage();
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exit(1);
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}
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if (strcmp(argv[0], "-") != 0) {
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input_filename = argv[0];
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input = fopen(input_filename, "r");
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if (input == NULL) {
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perror("Couldn't open input file");
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exit(1);
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}
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}
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program = read_program (input);
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if (!program)
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exit (1);
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if (output_file) {
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output = fopen (output_file, "w");
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if (output == NULL) {
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perror("Couldn't open output file");
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exit(1);
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}
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}
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for (inst = program->first; inst; inst = inst->next)
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disasm (output, &inst->instruction);
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exit (0);
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}
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554
assembler/src/disasm.c
Normal file
554
assembler/src/disasm.c
Normal file
@ -0,0 +1,554 @@
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/*
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* Copyright © 2008 Keith Packard
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*
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* Permission to use, copy, modify, distribute, and sell this software and its
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* documentation for any purpose is hereby granted without fee, provided that
|
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* the above copyright notice appear in all copies and that both that copyright
|
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* notice and this permission notice appear in supporting documentation, and
|
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* that the name of the copyright holders not be used in advertising or
|
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* publicity pertaining to distribution of the software without specific,
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* written prior permission. The copyright holders make no representations
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* about the suitability of this software for any purpose. It is provided "as
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* is" without express or implied warranty.
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*
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* THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
|
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* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
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* EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
|
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* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
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* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
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* OF THIS SOFTWARE.
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <getopt.h>
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#include <unistd.h>
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#include <stdarg.h>
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#include "gen4asm.h"
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#include "brw_defines.h"
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struct {
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char *name;
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int nsrc;
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int ndst;
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} opcode[128] = {
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[BRW_OPCODE_MOV] = { .name = "mov", .nsrc = 1, .ndst = 1 },
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[BRW_OPCODE_FRC] = { .name = "frc", .nsrc = 1, .ndst = 1 },
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[BRW_OPCODE_RNDU] = { .name = "rndu", .nsrc = 1, .ndst = 1 },
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[BRW_OPCODE_RNDD] = { .name = "rndd", .nsrc = 1, .ndst = 1 },
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[BRW_OPCODE_RNDE] = { .name = "rnde", .nsrc = 1, .ndst = 1 },
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[BRW_OPCODE_RNDZ] = { .name = "rndz", .nsrc = 1, .ndst = 1 },
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[BRW_OPCODE_NOT] = { .name = "not", .nsrc = 1, .ndst = 1 },
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[BRW_OPCODE_LZD] = { .name = "lzd", .nsrc = 1, .ndst = 1 },
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[BRW_OPCODE_MUL] = { .name = "mul", .nsrc = 2, .ndst = 1 },
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[BRW_OPCODE_MAC] = { .name = "mac", .nsrc = 2, .ndst = 1 },
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[BRW_OPCODE_MACH] = { .name = "mach", .nsrc = 2, .ndst = 1 },
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[BRW_OPCODE_LINE] = { .name = "line", .nsrc = 2, .ndst = 1 },
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[BRW_OPCODE_SAD2] = { .name = "sad2", .nsrc = 2, .ndst = 1 },
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[BRW_OPCODE_SADA2] = { .name = "sada2", .nsrc = 2, .ndst = 1 },
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[BRW_OPCODE_DP4] = { .name = "dp4", .nsrc = 2, .ndst = 1 },
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[BRW_OPCODE_DPH] = { .name = "dph", .nsrc = 2, .ndst = 1 },
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[BRW_OPCODE_DP3] = { .name = "dp3", .nsrc = 2, .ndst = 1 },
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[BRW_OPCODE_DP2] = { .name = "dp2", .nsrc = 2, .ndst = 1 },
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[BRW_OPCODE_AVG] = { .name = "avg", .nsrc = 2, .ndst = 1 },
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[BRW_OPCODE_ADD] = { .name = "add", .nsrc = 2, .ndst = 1 },
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[BRW_OPCODE_SEL] = { .name = "sel", .nsrc = 2, .ndst = 1 },
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[BRW_OPCODE_AND] = { .name = "and", .nsrc = 2, .ndst = 1 },
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[BRW_OPCODE_OR] = { .name = "or", .nsrc = 2, .ndst = 1 },
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[BRW_OPCODE_XOR] = { .name = "xor", .nsrc = 2, .ndst = 1 },
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[BRW_OPCODE_SHR] = { .name = "shr", .nsrc = 2, .ndst = 1 },
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[BRW_OPCODE_SHL] = { .name = "shl", .nsrc = 2, .ndst = 1 },
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[BRW_OPCODE_ASR] = { .name = "asr", .nsrc = 2, .ndst = 1 },
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[BRW_OPCODE_CMP] = { .name = "cmp", .nsrc = 2, .ndst = 1 },
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[BRW_OPCODE_CMPN] = { .name = "cmpn", .nsrc = 2, .ndst = 1 },
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[BRW_OPCODE_SEND] = { .name = "send", .nsrc = 1, .ndst = 1 },
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[BRW_OPCODE_NOP] = { .name = "nop", .nsrc = 0, .ndst = 0 },
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[BRW_OPCODE_JMPI] = { .name = "jmpi", .nsrc = 1, .ndst = 0 },
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[BRW_OPCODE_IF] = { .name = "if", .nsrc = 2, .ndst = 0 },
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[BRW_OPCODE_IFF] = { .name = "iff", .nsrc = 1, .ndst = 01 },
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[BRW_OPCODE_WHILE] = { .name = "while", .nsrc = 1, .ndst = 0 },
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[BRW_OPCODE_ELSE] = { .name = "else", .nsrc = 1, .ndst = 0 },
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[BRW_OPCODE_BREAK] = { .name = "break", .nsrc = 1, .ndst = 0 },
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[BRW_OPCODE_CONTINUE] = { .name = "cont", .nsrc = 1, .ndst = 0 },
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[BRW_OPCODE_HALT] = { .name = "halt", .nsrc = 1, .ndst = 0 },
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[BRW_OPCODE_MSAVE] = { .name = "msave", .nsrc = 1, .ndst = 1 },
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[BRW_OPCODE_PUSH] = { .name = "push", .nsrc = 1, .ndst = 1 },
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[BRW_OPCODE_MRESTORE] = { .name = "mrest", .nsrc = 1, .ndst = 1 },
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[BRW_OPCODE_POP] = { .name = "pop", .nsrc = 2, .ndst = 0 },
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[BRW_OPCODE_WAIT] = { .name = "wait", .nsrc = 1, .ndst = 0 },
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[BRW_OPCODE_DO] = { .name = "do", .nsrc = 0, .ndst = 0 },
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[BRW_OPCODE_ENDIF] = { .name = "endif", .nsrc = 0, .ndst = 0 },
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};
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char *conditional_modifier[16] = {
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[BRW_CONDITIONAL_NONE] = "",
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[BRW_CONDITIONAL_Z] = ".Z",
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[BRW_CONDITIONAL_NZ] = ".NZ",
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[BRW_CONDITIONAL_EQ] = ".EQ",
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[BRW_CONDITIONAL_NEQ] = ".NEQ",
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[BRW_CONDITIONAL_G] = ".G",
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[BRW_CONDITIONAL_GE] = ".GE",
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[BRW_CONDITIONAL_L] = ".L",
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[BRW_CONDITIONAL_LE] = ".LE",
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[BRW_CONDITIONAL_C] = ".C",
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[BRW_CONDITIONAL_O] = ".O",
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[BRW_CONDITIONAL_U] = ".U",
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};
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char *negate[2] = {
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[0] = "",
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[1] = "-",
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};
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char *_abs[2] = {
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[0] = "",
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[1] = "(abs)",
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};
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char *vert_stride[16] = {
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[0] = "0",
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[1] = "1",
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[2] = "2",
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[3] = "4",
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[4] = "8",
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[5] = "16",
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[6] = "32",
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[15] = "VxH",
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};
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char *width[8] = {
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[0] = "1",
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[1] = "2",
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[2] = "4",
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[3] = "8",
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[4] = "16",
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};
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char *horiz_stride[4] = {
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[0] = "0",
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[1] = "1",
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[2] = "2",
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[3] = "4"
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};
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char *chan_sel[4] = {
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[0] = "x",
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[1] = "y",
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[2] = "z",
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[3] = "w",
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};
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char *dest_condmod[16] = {
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};
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char *debug_ctrl[2] = {
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[0] = "",
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[1] = ".breakpoint"
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};
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char *saturate[2] = {
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[0] = "",
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[1] = ".sat"
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};
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char *exec_size[8] = {
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[0] = "1",
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[1] = "2",
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[2] = "4",
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[3] = "8",
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[4] = "16",
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[5] = "32"
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};
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char *pred_inv[2] = {
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[0] = "+",
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[1] = "-"
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};
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char *pred_ctrl_align16[16] = {
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[0] = "",
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[1] = "sequential",
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[2] = "replication swizzle .x",
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[3] = "replication swizzle .y",
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[4] = "replication swizzle .z",
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[5] = "replication swizzle .w",
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[6] = ".any4h",
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[7] = ".all4h",
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};
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char *pred_ctrl_align1[16] = {
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[0] = "",
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[1] = "sequential",
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[2] = ".anyv",
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[3] = ".allv",
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[4] = ".any2h",
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[5] = ".all2h",
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[6] = ".any4h",
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[7] = ".all4h",
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[8] = ".any8h",
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[9] = ".all8h",
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[10] = ".any16h",
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[11] = ".all16h",
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};
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char *thread_ctrl[4] = {
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[0] = "",
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[2] = "switch"
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};
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char *compr_ctrl[4] = {
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[0] = "",
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[1] = "sechalf",
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[2] = "compr",
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};
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char *dep_ctrl[4] = {
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[0] = "",
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[1] = "NoDDClr",
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[2] = "NoDDChk",
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[3] = "NoDDClr,NoDDChk",
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};
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char *mask_ctrl[4] = {
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[0] = "",
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[1] = "nomask",
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};
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char *access_mode[2] = {
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[0] = "align1",
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[1] = "align16",
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};
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char *reg_encoding[8] = {
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[0] = "UD",
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[1] = "D",
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[2] = "UW",
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[3] = "W",
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[4] = "UB",
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[5] = "B",
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[7] = "F"
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};
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char *imm_encoding[8] = {
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[0] = "UD",
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[1] = "D",
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[2] = "UW",
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[3] = "W",
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[5] = "VF",
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[5] = "V",
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[7] = "F"
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};
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char *reg_file[4] = {
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[0] = "A",
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[1] = "g",
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[2] = "m",
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[3] = "imm",
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};
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char *end_of_thread[2] = {
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[0] = "",
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[1] = "EOT"
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};
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char *target_function[16] = {
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[BRW_MESSAGE_TARGET_NULL] = "null",
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[BRW_MESSAGE_TARGET_MATH] = "math",
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[BRW_MESSAGE_TARGET_SAMPLER] = "sampler",
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[BRW_MESSAGE_TARGET_GATEWAY] = "gateway",
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[BRW_MESSAGE_TARGET_DATAPORT_READ] = "read",
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[BRW_MESSAGE_TARGET_DATAPORT_WRITE] = "write",
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[BRW_MESSAGE_TARGET_URB] = "urb",
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[BRW_MESSAGE_TARGET_THREAD_SPAWNER] = "thread_spawner"
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};
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char *sampler_target_format[4] = {
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[0] = "F",
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[2] = "UD",
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[3] = "D"
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};
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static int column;
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static int string (FILE *file, char *string)
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{
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fputs (string, file);
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column += strlen (string);
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return 0;
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}
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static int format (FILE *f, char *format, ...)
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{
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char buf[1024];
|
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va_list args;
|
||||
va_start (args, format);
|
||||
|
||||
vsnprintf (buf, sizeof (buf) - 1, format, args);
|
||||
string (f, buf);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int newline (FILE *f)
|
||||
{
|
||||
putc ('\n', f);
|
||||
column = 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pad (FILE *f, int c)
|
||||
{
|
||||
while (column < c)
|
||||
string (f, " ");
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int control (FILE *file, char *name, char *ctrl[], GLuint id, int *space)
|
||||
{
|
||||
if (!ctrl[id]) {
|
||||
fprintf (file, "*** invalid %s value %d ",
|
||||
name, id);
|
||||
return 1;
|
||||
}
|
||||
if (ctrl[id][0])
|
||||
{
|
||||
if (space && *space)
|
||||
string (file, " ");
|
||||
string (file, ctrl[id]);
|
||||
if (space)
|
||||
*space = 1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int print_opcode (FILE *file, int id)
|
||||
{
|
||||
if (!opcode[id].name) {
|
||||
format (file, "*** invalid opcode value %d ", id);
|
||||
return 1;
|
||||
}
|
||||
string (file, opcode[id].name);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int dest (FILE *file, struct brw_instruction *inst)
|
||||
{
|
||||
int err = 0;
|
||||
|
||||
if (inst->bits1.da1.dest_reg_file == BRW_ARCHITECTURE_REGISTER_FILE) {
|
||||
switch (inst->bits1.da1.dest_reg_nr & 0xf0) {
|
||||
case BRW_ARF_NULL:
|
||||
string (file, "null");
|
||||
return 0;
|
||||
case BRW_ARF_ADDRESS:
|
||||
format (file, "a%d", inst->bits1.da1.dest_reg_nr & 0x0f);
|
||||
break;
|
||||
case BRW_ARF_ACCUMULATOR:
|
||||
format (file, "acc%d", inst->bits1.da1.dest_reg_nr & 0x0f);
|
||||
break;
|
||||
case BRW_ARF_MASK:
|
||||
format (file, "mask%d", inst->bits1.da1.dest_reg_nr & 0x0f);
|
||||
break;
|
||||
case BRW_ARF_MASK_STACK:
|
||||
format (file, "msd%d", inst->bits1.da1.dest_reg_nr & 0x0f);
|
||||
break;
|
||||
case BRW_ARF_STATE:
|
||||
format (file, "sr%d", inst->bits1.da1.dest_reg_nr & 0x0f);
|
||||
break;
|
||||
case BRW_ARF_CONTROL:
|
||||
format (file, "cr%d", inst->bits1.da1.dest_reg_nr & 0x0f);
|
||||
break;
|
||||
case BRW_ARF_NOTIFICATION_COUNT:
|
||||
format (file, "n%d", inst->bits1.da1.dest_reg_nr & 0x0f);
|
||||
break;
|
||||
case BRW_ARF_IP:
|
||||
string (file, "ip");
|
||||
break;
|
||||
default:
|
||||
format (file, "ARF%d", inst->bits1.da1.dest_reg_nr);
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
err |= control (file, "dest reg file", reg_file, inst->bits1.da1.dest_reg_file, NULL);
|
||||
format (file, "%d", inst->bits1.da1.dest_reg_nr);
|
||||
}
|
||||
if (inst->bits1.da1.dest_subreg_nr)
|
||||
format (file, ".%d", inst->bits1.da1.dest_subreg_nr);
|
||||
format (file, "<%d>", inst->bits1.da1.dest_horiz_stride);
|
||||
err |= control (file, "dest reg encoding", reg_encoding, inst->bits1.da1.dest_reg_type, NULL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int src (FILE *file, GLuint type, GLuint _reg_file,
|
||||
GLuint _vert_stride, GLuint _width, GLuint _horiz_stride,
|
||||
GLuint reg_num, GLuint sub_reg_num)
|
||||
{
|
||||
int err = 0;
|
||||
err |= control (file, "src reg file", reg_file, _reg_file, NULL);
|
||||
format (file, "%d", reg_num);
|
||||
if (sub_reg_num)
|
||||
format (file, ".%d", sub_reg_num);
|
||||
string (file, "<");
|
||||
err |= control (file, "vert stride", vert_stride, _vert_stride, NULL);
|
||||
string (file, ",");
|
||||
err |= control (file, "width", width, _width, NULL);
|
||||
string (file, ",");
|
||||
err |= control (file, "horiz_stride", horiz_stride, _horiz_stride, NULL);
|
||||
string (file, ">");
|
||||
err |= control (file, "src reg encoding", reg_encoding, type, NULL);
|
||||
return err;
|
||||
}
|
||||
|
||||
static int imm (FILE *file, GLuint type, struct brw_instruction *inst) {
|
||||
switch (type) {
|
||||
case BRW_REGISTER_TYPE_UD:
|
||||
format (file, "0x%08xUD", inst->bits3.ud);
|
||||
break;
|
||||
case BRW_REGISTER_TYPE_D:
|
||||
format (file, "%dD", inst->bits3.id);
|
||||
break;
|
||||
case BRW_REGISTER_TYPE_UW:
|
||||
format (file, "0x%04xUW", (uint16_t) inst->bits3.ud);
|
||||
break;
|
||||
case BRW_REGISTER_TYPE_W:
|
||||
format (file, "%dW", (int16_t) inst->bits3.id);
|
||||
break;
|
||||
case BRW_REGISTER_TYPE_UB:
|
||||
format (file, "0x%02xUB", (int8_t) inst->bits3.ud);
|
||||
break;
|
||||
case BRW_REGISTER_TYPE_VF:
|
||||
format (file, "Vector Float");
|
||||
break;
|
||||
case BRW_REGISTER_TYPE_V:
|
||||
format (file, "0x%08xV", inst->bits3.ud);
|
||||
break;
|
||||
case BRW_REGISTER_TYPE_F:
|
||||
format (file, "%-gF", inst->bits3.fd);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int src0 (FILE *file, struct brw_instruction *inst)
|
||||
{
|
||||
if (inst->bits1.da1.src0_reg_file == BRW_IMMEDIATE_VALUE)
|
||||
return imm (file, inst->bits1.da1.src0_reg_type,
|
||||
inst);
|
||||
else
|
||||
return src (file,
|
||||
inst->bits1.da1.src0_reg_type,
|
||||
inst->bits1.da1.src0_reg_file,
|
||||
inst->bits2.da1.src0_vert_stride,
|
||||
inst->bits2.da1.src0_width,
|
||||
inst->bits2.da1.src0_horiz_stride,
|
||||
inst->bits2.da1.src0_reg_nr,
|
||||
inst->bits2.da1.src0_subreg_nr);
|
||||
}
|
||||
|
||||
static int src1 (FILE *file, struct brw_instruction *inst)
|
||||
{
|
||||
if (inst->bits1.da1.src1_reg_file == BRW_IMMEDIATE_VALUE)
|
||||
return imm (file, inst->bits1.da1.src1_reg_type,
|
||||
inst);
|
||||
else
|
||||
return src (file,
|
||||
inst->bits1.da1.src1_reg_type,
|
||||
inst->bits1.da1.src1_reg_file,
|
||||
inst->bits3.da1.src1_vert_stride,
|
||||
inst->bits3.da1.src1_width,
|
||||
inst->bits3.da1.src1_horiz_stride,
|
||||
inst->bits3.da1.src1_reg_nr,
|
||||
inst->bits3.da1.src1_subreg_nr);
|
||||
}
|
||||
|
||||
int disasm (FILE *file, struct brw_instruction *inst)
|
||||
{
|
||||
int err = 0;
|
||||
int space = 0;
|
||||
|
||||
if (inst->header.predicate_control || inst->header.predicate_inverse) {
|
||||
string (file, "(");
|
||||
space = 0;
|
||||
err |= control (file, "predicate inverse", pred_inv, inst->header.predicate_inverse, &space);
|
||||
if (inst->header.access_mode == BRW_ALIGN_1)
|
||||
err |= control (file, "predicate control align1", pred_ctrl_align1,
|
||||
inst->header.predicate_control, &space);
|
||||
else
|
||||
err |= control (file, "predicate control align16", pred_ctrl_align16,
|
||||
inst->header.predicate_control, &space);
|
||||
}
|
||||
|
||||
err |= print_opcode (file, inst->header.opcode);
|
||||
err |= control (file, "saturate", saturate, inst->header.saturate, NULL);
|
||||
err |= control (file, "debug control", debug_ctrl, inst->header.debug_control, NULL);
|
||||
|
||||
string (file, "("); {
|
||||
err |= control (file, "execution size", exec_size, inst->header.execution_size, NULL);
|
||||
} string (file, ")");
|
||||
|
||||
if (inst->header.opcode == BRW_OPCODE_SEND) {
|
||||
format (file, " %d", inst->header.destreg__conditionalmod);
|
||||
space = 1;
|
||||
format (file, " mlen %d",
|
||||
inst->bits3.generic.msg_length);
|
||||
format (file, " rlen %d",
|
||||
inst->bits3.generic.response_length);
|
||||
err |= control (file, "end of thread", end_of_thread,
|
||||
inst->bits3.generic.end_of_thread, &space);
|
||||
err |= control (file, "target function", target_function,
|
||||
inst->bits3.generic.msg_target, &space);
|
||||
switch (inst->bits3.generic.msg_target) {
|
||||
case BRW_MESSAGE_TARGET_SAMPLER:
|
||||
format (file, "( %d, %d, ",
|
||||
inst->bits3.sampler.binding_table_index,
|
||||
inst->bits3.sampler.sampler);
|
||||
err |= control (file, "sampler target format", sampler_target_format,
|
||||
inst->bits3.sampler.return_format, NULL);
|
||||
string (file, " )");
|
||||
break;
|
||||
case BRW_MESSAGE_TARGET_DATAPORT_WRITE:
|
||||
format (file, "( %d, %d, %d, %d )",
|
||||
inst->bits3.dp_write.binding_table_index,
|
||||
inst->bits3.dp_write.pixel_scoreboard_clear << 3 |
|
||||
inst->bits3.dp_write.msg_control,
|
||||
inst->bits3.dp_write.msg_type,
|
||||
inst->bits3.dp_write.send_commit_msg);
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
err |= control (file, "conditional modifier", conditional_modifier,
|
||||
inst->header.destreg__conditionalmod, NULL);
|
||||
|
||||
if (opcode[inst->header.opcode].ndst > 0) {
|
||||
pad (file, 16);
|
||||
err |= dest (file, inst);
|
||||
}
|
||||
if (opcode[inst->header.opcode].nsrc > 0) {
|
||||
pad (file, 32);
|
||||
err |= src0 (file, inst);
|
||||
}
|
||||
if (opcode[inst->header.opcode].nsrc > 1) {
|
||||
pad (file, 48);
|
||||
err |= src1 (file, inst);
|
||||
}
|
||||
pad (file, 64);
|
||||
string (file, "{"); {
|
||||
space = 1;
|
||||
err |= control(file, "access mode", access_mode, inst->header.access_mode, &space);
|
||||
err |= control (file, "mask control", mask_ctrl, inst->header.mask_control, &space);
|
||||
err |= control (file, "dependency control", dep_ctrl, inst->header.dependency_control, &space);
|
||||
err |= control (file, "compression control", compr_ctrl, inst->header.compression_control, &space);
|
||||
err |= control (file, "thread control", thread_ctrl, inst->header.thread_control, &space);
|
||||
if (space)
|
||||
string (file, " ");
|
||||
} string (file, "};");
|
||||
newline (file);
|
||||
return err;
|
||||
}
|
||||
@ -128,3 +128,6 @@ int yylex(void);
|
||||
|
||||
char *
|
||||
lex_text(void);
|
||||
|
||||
int
|
||||
disasm (FILE *output, struct brw_instruction *inst);
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user