mirror of
https://github.com/tiagovignatti/intel-gpu-tools.git
synced 2025-06-10 17:36:11 +00:00
Quieten valgrind
Clear all the ioctl structs to zero before use as valgrind does not our ioctls and so complains about undefined bytes being passed to syscalls. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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acca724b42
@ -77,8 +77,9 @@ static int
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is_intel(int fd)
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{
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struct drm_i915_getparam gp;
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int devid;
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int devid = 0;
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memset(&gp, 0, sizeof(gp));
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gp.param = I915_PARAM_CHIPSET_ID;
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gp.value = &devid;
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@ -130,15 +130,17 @@ intel_get_pci_device(void)
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uint32_t
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intel_get_drm_devid(int fd)
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{
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int ret;
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struct drm_i915_getparam gp;
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uint32_t devid;
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char *override;
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uint32_t devid = 0;
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const char *override;
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override = getenv("INTEL_DEVID_OVERRIDE");
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if (override) {
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devid = strtod(override, NULL);
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} else {
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struct drm_i915_getparam gp;
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int ret;
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memset(&gp, 0, sizeof(gp));
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gp.param = I915_PARAM_CHIPSET_ID;
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gp.value = (int *)&devid;
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@ -97,6 +97,7 @@ gem_handle_to_libdrm_bo(drm_intel_bufmgr *bufmgr, int fd, const char *name, uint
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int ret;
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drm_intel_bo *bo;
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memset(&flink, 0, sizeof(handle));
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flink.handle = handle;
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ret = ioctl(fd, DRM_IOCTL_GEM_FLINK, &flink);
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igt_assert(ret == 0);
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@ -196,6 +197,7 @@ void gem_set_caching(int fd, uint32_t handle, uint32_t caching)
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struct local_drm_i915_gem_caching arg;
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int ret;
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memset(&arg, 0, sizeof(arg));
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arg.handle = handle;
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arg.caching = caching;
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ret = ioctl(fd, LOCAL_DRM_IOCTL_I915_GEM_SET_CACHEING, &arg);
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@ -242,6 +244,7 @@ uint32_t gem_open(int fd, uint32_t name)
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struct drm_gem_open open_struct;
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int ret;
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memset(&open_struct, 0, sizeof(open_struct));
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open_struct.name = name;
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ret = ioctl(fd, DRM_IOCTL_GEM_OPEN, &open_struct);
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igt_assert(ret == 0);
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@ -267,6 +270,7 @@ uint32_t gem_flink(int fd, uint32_t handle)
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struct drm_gem_flink flink;
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int ret;
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memset(&flink, 0, sizeof(flink));
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flink.handle = handle;
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ret = ioctl(fd, DRM_IOCTL_GEM_FLINK, &flink);
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igt_assert(ret == 0);
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@ -287,6 +291,7 @@ void gem_close(int fd, uint32_t handle)
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{
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struct drm_gem_close close_bo;
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memset(&close_bo, 0, sizeof(close_bo));
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close_bo.handle = handle;
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do_ioctl(fd, DRM_IOCTL_GEM_CLOSE, &close_bo);
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}
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@ -306,6 +311,7 @@ void gem_write(int fd, uint32_t handle, uint32_t offset, const void *buf, uint32
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{
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struct drm_i915_gem_pwrite gem_pwrite;
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memset(&gem_pwrite, 0, sizeof(gem_pwrite));
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gem_pwrite.handle = handle;
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gem_pwrite.offset = offset;
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gem_pwrite.size = length;
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@ -328,6 +334,7 @@ void gem_read(int fd, uint32_t handle, uint32_t offset, void *buf, uint32_t leng
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{
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struct drm_i915_gem_pread gem_pread;
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memset(&gem_pread, 0, sizeof(gem_pread));
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gem_pread.handle = handle;
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gem_pread.offset = offset;
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gem_pread.size = length;
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@ -352,6 +359,7 @@ void gem_set_domain(int fd, uint32_t handle,
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{
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struct drm_i915_gem_set_domain set_domain;
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memset(&set_domain, 0, sizeof(set_domain));
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set_domain.handle = handle;
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set_domain.read_domains = read_domains;
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set_domain.write_domain = write_domain;
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@ -377,6 +385,7 @@ uint32_t __gem_create(int fd, int size)
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struct drm_i915_gem_create create;
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int ret;
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memset(&create, 0, sizeof(create));
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create.handle = 0;
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create.size = size;
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ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_CREATE, &create);
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@ -402,6 +411,7 @@ uint32_t gem_create(int fd, int size)
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{
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struct drm_i915_gem_create create;
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memset(&create, 0, sizeof(create));
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create.handle = 0;
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create.size = size;
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do_ioctl(fd, DRM_IOCTL_I915_GEM_CREATE, &create);
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@ -446,6 +456,7 @@ void *gem_mmap__gtt(int fd, uint32_t handle, int size, int prot)
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struct drm_i915_gem_mmap_gtt mmap_arg;
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void *ptr;
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memset(&mmap_arg, 0, sizeof(mmap_arg));
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mmap_arg.handle = handle;
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if (drmIoctl(fd, DRM_IOCTL_I915_GEM_MMAP_GTT, &mmap_arg))
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return NULL;
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@ -473,6 +484,7 @@ void *gem_mmap__cpu(int fd, uint32_t handle, int size, int prot)
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{
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struct drm_i915_gem_mmap mmap_arg;
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memset(&mmap_arg, 0, sizeof(mmap_arg));
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mmap_arg.handle = handle;
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mmap_arg.offset = 0;
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mmap_arg.size = size;
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@ -501,6 +513,7 @@ int gem_madvise(int fd, uint32_t handle, int state)
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{
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struct drm_i915_gem_madvise madv;
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memset(&madv, 0, sizeof(madv));
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madv.handle = handle;
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madv.madv = state;
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madv.retained = 1;
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@ -525,6 +538,7 @@ uint32_t gem_context_create(int fd)
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struct drm_i915_gem_context_create create;
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int ret;
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memset(&create, 0, sizeof(create));
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ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_CONTEXT_CREATE, &create);
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igt_require(ret == 0 || (errno != ENODEV && errno != EINVAL));
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igt_assert(ret == 0);
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@ -546,6 +560,7 @@ void gem_sw_finish(int fd, uint32_t handle)
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{
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struct drm_i915_gem_sw_finish finish;
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memset(&finish, 0, sizeof(finish));
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finish.handle = handle;
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do_ioctl(fd, DRM_IOCTL_I915_GEM_SW_FINISH, &finish);
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@ -565,6 +580,7 @@ bool gem_bo_busy(int fd, uint32_t handle)
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{
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struct drm_i915_gem_busy busy;
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memset(&busy, 0, sizeof(busy));
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busy.handle = handle;
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do_ioctl(fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
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@ -590,8 +606,9 @@ bool gem_bo_busy(int fd, uint32_t handle)
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bool gem_uses_aliasing_ppgtt(int fd)
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{
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struct drm_i915_getparam gp;
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int val;
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int val = 0;
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memset(&gp, 0, sizeof(gp));
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gp.param = 18; /* HAS_ALIASING_PPGTT */
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gp.value = &val;
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@ -614,8 +631,9 @@ bool gem_uses_aliasing_ppgtt(int fd)
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int gem_available_fences(int fd)
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{
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struct drm_i915_getparam gp;
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int val;
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int val = 0;
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memset(&gp, 0, sizeof(gp));
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gp.param = I915_PARAM_NUM_FENCES_AVAIL;
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gp.value = &val;
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@ -674,9 +692,9 @@ skip:
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bool gem_has_enable_ring(int fd,int param)
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{
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drm_i915_getparam_t gp;
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int tmp;
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memset(&gp, 0, sizeof(gp));
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int tmp = 0;
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memset(&gp, 0, sizeof(gp));
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gp.value = &tmp;
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gp.param = param;
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@ -716,7 +734,6 @@ bool gem_has_bsd(int fd)
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*/
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bool gem_has_blt(int fd)
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{
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return gem_has_enable_ring(fd,I915_PARAM_HAS_BLT);
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}
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@ -735,7 +752,6 @@ bool gem_has_blt(int fd)
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*/
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bool gem_has_vebox(int fd)
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{
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return gem_has_enable_ring(fd,LOCAL_I915_PARAM_HAS_VEBOX);
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}
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@ -752,8 +768,10 @@ uint64_t gem_available_aperture_size(int fd)
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{
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struct drm_i915_gem_get_aperture aperture;
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memset(&aperture, 0, sizeof(aperture));
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aperture.aper_size = 256*1024*1024;
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do_ioctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
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return aperture.aper_available_size;
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}
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@ -769,8 +787,10 @@ uint64_t gem_aperture_size(int fd)
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{
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struct drm_i915_gem_get_aperture aperture;
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memset(&aperture, 0, sizeof(aperture));
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aperture.aper_size = 256*1024*1024;
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do_ioctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
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return aperture.aper_size;
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}
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@ -785,9 +805,8 @@ uint64_t gem_aperture_size(int fd)
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*/
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uint64_t gem_mappable_aperture_size(void)
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{
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struct pci_device *pci_dev;
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struct pci_device *pci_dev = intel_get_pci_device();
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int bar;
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pci_dev = intel_get_pci_device();
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if (intel_gen(pci_dev->device_id) < 3)
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bar = 0;
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@ -809,6 +828,7 @@ void gem_require_caching(int fd)
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struct local_drm_i915_gem_caching arg;
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int ret;
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memset(&arg, 0, sizeof(arg));
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arg.handle = gem_create(fd, 4096);
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igt_assert(arg.handle != 0);
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@ -868,6 +888,7 @@ int prime_handle_to_fd(int fd, uint32_t handle)
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{
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struct drm_prime_handle args;
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memset(&args, 0, sizeof(args));
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args.handle = handle;
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args.flags = DRM_CLOEXEC;
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args.fd = -1;
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@ -891,6 +912,7 @@ uint32_t prime_fd_to_handle(int fd, int dma_buf_fd)
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{
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struct drm_prime_handle args;
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memset(&args, 0, sizeof(args));
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args.fd = dma_buf_fd;
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args.flags = 0;
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args.handle = 0;
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@ -913,6 +935,7 @@ uint32_t prime_fd_to_handle(int fd, int dma_buf_fd)
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off_t prime_get_size(int dma_buf_fd)
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{
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off_t ret;
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ret = lseek(dma_buf_fd, 0, SEEK_END);
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igt_assert(ret >= 0 || errno == ESPIPE);
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igt_require(ret >= 0);
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