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tests/gem_cacheing: Exercise snoop coherency
This is based on tests/gem_partial_pwrite_pread which aims to detect incoherency between CPU reads and writes to a bo whilst using it as a source and target for GPU writes. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Chris Wilson
parent
51baabb562
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ac23daaa51
1
tests/.gitignore
vendored
1
tests/.gitignore
vendored
@ -8,6 +8,7 @@ gem_bad_batch
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gem_bad_blit
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gem_bad_length
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gem_basic
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gem_cacheing
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gem_cs_prefetch
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gem_cpu_concurrent_blit
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gem_ctx_bad_destroy
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@ -16,6 +16,7 @@ TESTS_progs = \
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getclient \
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getstats \
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gem_basic \
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gem_cacheing \
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gem_cpu_concurrent_blit \
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gem_gtt_concurrent_blit \
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gem_exec_nop \
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290
tests/gem_cacheing.c
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290
tests/gem_cacheing.c
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@ -0,0 +1,290 @@
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/*
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* Copyright © 2012 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Daniel Vetter <daniel.vetter@ffwll.ch>
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* Chris Wilson <chris@chris-wilson.co.uk>
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*
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*/
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <assert.h>
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#include <fcntl.h>
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#include <inttypes.h>
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#include <errno.h>
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#include <sys/stat.h>
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#include <sys/time.h>
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#include "drm.h"
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#include "i915_drm.h"
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#include "drmtest.h"
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#include "intel_bufmgr.h"
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#include "intel_batchbuffer.h"
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#include "intel_gpu_tools.h"
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/*
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* Testcase: snoop consistency when touching partial cachelines
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*
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*/
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static drm_intel_bufmgr *bufmgr;
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struct intel_batchbuffer *batch;
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drm_intel_bo *scratch_bo;
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drm_intel_bo *staging_bo;
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#define BO_SIZE (4*4096)
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uint32_t devid;
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uint64_t mappable_gtt_limit;
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int fd;
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static void
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copy_bo(drm_intel_bo *src, drm_intel_bo *dst)
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{
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BEGIN_BATCH(8);
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OUT_BATCH(XY_SRC_COPY_BLT_CMD |
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XY_SRC_COPY_BLT_WRITE_ALPHA |
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XY_SRC_COPY_BLT_WRITE_RGB);
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OUT_BATCH((3 << 24) | /* 32 bits */
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(0xcc << 16) | /* copy ROP */
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4096);
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OUT_BATCH(0 << 16 | 0);
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OUT_BATCH((BO_SIZE/4096) << 16 | 1024);
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OUT_RELOC_FENCED(dst, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
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OUT_BATCH(0 << 16 | 0);
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OUT_BATCH(4096);
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OUT_RELOC_FENCED(src, I915_GEM_DOMAIN_RENDER, 0, 0);
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ADVANCE_BATCH();
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intel_batchbuffer_flush(batch);
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}
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static void
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blt_bo_fill(drm_intel_bo *tmp_bo, drm_intel_bo *bo, uint8_t val)
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{
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uint8_t *gtt_ptr;
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int i;
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do_or_die(drm_intel_gem_bo_map_gtt(tmp_bo));
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gtt_ptr = tmp_bo->virtual;
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for (i = 0; i < BO_SIZE; i++)
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gtt_ptr[i] = val;
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drm_intel_gem_bo_unmap_gtt(tmp_bo);
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if (bo->offset < mappable_gtt_limit &&
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(IS_G33(devid) || intel_gen(devid) >= 4))
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drmtest_trash_aperture();
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copy_bo(tmp_bo, bo);
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}
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#define MAX_BLT_SIZE 128
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#define ROUNDS 1000
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#define TEST_READ 0x1
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#define TEST_WRITE 0x2
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#define TEST_BOTH (TEST_READ | TEST_WRITE)
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int main(int argc, char **argv)
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{
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unsigned flags = TEST_BOTH;
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int i, j;
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uint8_t *cpu_ptr;
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uint8_t *gtt_ptr;
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srandom(0xdeadbeef);
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fd = drm_open_any();
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if (!gem_has_cacheing(fd))
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return 77;
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devid = intel_get_drm_devid(fd);
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if (IS_GEN2(devid)) /* chipset only handles cached -> uncached */
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flags &= ~TEST_READ;
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if (IS_965(devid)) /* chipset is completely fubar */
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flags = 0;
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if (flags == 0)
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return 77;
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bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
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batch = intel_batchbuffer_alloc(bufmgr, devid);
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/* overallocate the buffers we're actually using because */
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scratch_bo = drm_intel_bo_alloc(bufmgr, "scratch bo", BO_SIZE, 4096);
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gem_set_cacheing(fd, scratch_bo->handle, 1);
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staging_bo = drm_intel_bo_alloc(bufmgr, "staging bo", BO_SIZE, 4096);
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drmtest_init_aperture_trashers(bufmgr);
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mappable_gtt_limit = gem_mappable_aperture_size();
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if (flags & TEST_READ) {
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printf("checking partial reads\n");
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for (i = 0; i < ROUNDS; i++) {
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uint8_t val0 = i;
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int start, len;
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blt_bo_fill(staging_bo, scratch_bo, i);
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start = random() % BO_SIZE;
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len = random() % (BO_SIZE-start) + 1;
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drm_intel_bo_map(scratch_bo, false);
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cpu_ptr = scratch_bo->virtual;
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for (j = 0; j < len; j++) {
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if (cpu_ptr[j] != val0) {
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printf("mismatch at %i, got: %i, expected: %i\n",
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j, cpu_ptr[j], val0);
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exit(1);
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}
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}
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drm_intel_bo_unmap(scratch_bo);
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drmtest_progress("partial reads test: ", i, ROUNDS);
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}
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}
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if (flags & TEST_WRITE) {
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printf("checking partial writes\n");
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for (i = 0; i < ROUNDS; i++) {
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uint8_t val0 = i, val1;
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int start, len;
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blt_bo_fill(staging_bo, scratch_bo, val0);
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start = random() % BO_SIZE;
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len = random() % (BO_SIZE-start) + 1;
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val1 = val0 + 63;
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drm_intel_bo_map(scratch_bo, true);
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cpu_ptr = scratch_bo->virtual;
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memset(cpu_ptr + start, val1, len);
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drm_intel_bo_unmap(scratch_bo);
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copy_bo(scratch_bo, staging_bo);
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do_or_die(drm_intel_gem_bo_map_gtt(staging_bo));
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gtt_ptr = staging_bo->virtual;
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for (j = 0; j < start; j++) {
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if (gtt_ptr[j] != val0) {
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printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
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j, start, len, gtt_ptr[j], val0);
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exit(1);
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}
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}
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for (; j < start + len; j++) {
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if (gtt_ptr[j] != val1) {
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printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
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j, start, len, gtt_ptr[j], val1);
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exit(1);
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}
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}
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for (; j < BO_SIZE; j++) {
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if (gtt_ptr[j] != val0) {
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printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
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j, start, len, gtt_ptr[j], val0);
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exit(1);
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}
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}
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drm_intel_gem_bo_unmap_gtt(staging_bo);
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drmtest_progress("partial writes test: ", i, ROUNDS);
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}
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}
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if ((flags & TEST_BOTH) == TEST_BOTH) {
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printf("checking partial writes after partial reads\n");
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for (i = 0; i < ROUNDS; i++) {
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uint8_t val0 = i, val1, val2;
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int start, len;
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blt_bo_fill(staging_bo, scratch_bo, val0);
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/* partial read */
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start = random() % BO_SIZE;
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len = random() % (BO_SIZE-start) + 1;
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do_or_die(drm_intel_bo_map(scratch_bo, false));
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cpu_ptr = scratch_bo->virtual;
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for (j = 0; j < len; j++) {
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if (cpu_ptr[j] != val0) {
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printf("mismatch in read at %i, got: %i, expected: %i\n",
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j, cpu_ptr[j], val0);
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exit(1);
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}
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}
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drm_intel_bo_unmap(scratch_bo);
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/* Change contents through gtt to make the pread cachelines
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* stale. */
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val1 = i + 17;
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blt_bo_fill(staging_bo, scratch_bo, val1);
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/* partial write */
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start = random() % BO_SIZE;
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len = random() % (BO_SIZE-start) + 1;
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val2 = i + 63;
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do_or_die(drm_intel_bo_map(scratch_bo, false));
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cpu_ptr = scratch_bo->virtual;
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memset(cpu_ptr + start, val2, len);
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copy_bo(scratch_bo, staging_bo);
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do_or_die(drm_intel_gem_bo_map_gtt(staging_bo));
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gtt_ptr = staging_bo->virtual;
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for (j = 0; j < start; j++) {
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if (gtt_ptr[j] != val1) {
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printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
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j, start, len, gtt_ptr[j], val1);
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exit(1);
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}
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}
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for (; j < start + len; j++) {
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if (gtt_ptr[j] != val2) {
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printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
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j, start, len, gtt_ptr[j], val2);
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exit(1);
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}
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}
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for (; j < BO_SIZE; j++) {
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if (gtt_ptr[j] != val1) {
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printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
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j, start, len, gtt_ptr[j], val1);
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exit(1);
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}
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}
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drm_intel_gem_bo_unmap_gtt(staging_bo);
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drm_intel_bo_unmap(scratch_bo);
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drmtest_progress("partial read/writes test: ", i, ROUNDS);
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}
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}
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drmtest_cleanup_aperture_trashers();
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drm_intel_bufmgr_destroy(bufmgr);
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close(fd);
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return 0;
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}
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