mirror of
https://github.com/tiagovignatti/intel-gpu-tools.git
synced 2025-06-10 09:26:10 +00:00
lib/gpgpu_fill: Add BDW support
BDW changed structure of surface state and interface descriptors. Commands like state base address, gpgpu walker were extended. Cc: Thomas Wood <thomas.wood@intel.com> Signed-off-by: Dominik Zeromski <dominik.zeromski@intel.com> Signed-off-by: Thomas Wood <thomas.wood@intel.com>
This commit is contained in:
Dominik Zeromski
Thomas Wood
parent
ed816d560c
commit
a017c2905a
296
lib/gpgpu_fill.c
296
lib/gpgpu_fill.c
@ -32,6 +32,7 @@
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#include "drmtest.h"
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#include "intel_batchbuffer.h"
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#include "gen7_media.h"
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#include "gen8_media.h"
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#include "gpgpu_fill.h"
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/* shaders/gpgpu/gpgpu_fill.gxa */
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@ -48,6 +49,19 @@ static const uint32_t gen7_gpgpu_kernel[][4] = {
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{ 0x07800031, 0x20001ca8, 0x00000e00, 0x82000010 },
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};
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static const uint32_t gen8_gpgpu_kernel[][4] = {
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{ 0x00400001, 0x20202288, 0x00000020, 0x00000000 },
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{ 0x00000041, 0x20400208, 0x06000004, 0x00000010 },
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{ 0x00000001, 0x20440208, 0x00000018, 0x00000000 },
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{ 0x00600001, 0x20800208, 0x008d0000, 0x00000000 },
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{ 0x00200001, 0x20800208, 0x00450040, 0x00000000 },
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{ 0x00000001, 0x20880608, 0x00000000, 0x0000000f },
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{ 0x00800001, 0x20a00208, 0x00000020, 0x00000000 },
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{ 0x0c800031, 0x24000a40, 0x0e000080, 0x060a8000 },
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{ 0x00600001, 0x2e000208, 0x008d0000, 0x00000000 },
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{ 0x07800031, 0x20000a40, 0x0e000e00, 0x82000010 },
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};
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static uint32_t
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batch_used(struct intel_batchbuffer *batch)
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{
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@ -97,8 +111,7 @@ gen7_render_flush(struct intel_batchbuffer *batch, uint32_t batch_end)
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}
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static uint32_t
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gen7_fill_curbe_buffer_data(struct intel_batchbuffer *batch,
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uint8_t color)
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gen7_fill_curbe_buffer_data(struct intel_batchbuffer *batch, uint8_t color)
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{
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uint8_t *curbe_buffer;
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uint32_t offset;
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@ -159,6 +172,58 @@ gen7_fill_surface_state(struct intel_batchbuffer *batch,
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return offset;
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}
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static uint32_t
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gen8_fill_surface_state(struct intel_batchbuffer *batch,
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struct igt_buf *buf,
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uint32_t format,
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int is_dst)
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{
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struct gen8_surface_state *ss;
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uint32_t write_domain, read_domain, offset;
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int ret;
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if (is_dst) {
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write_domain = read_domain = I915_GEM_DOMAIN_RENDER;
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} else {
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write_domain = 0;
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read_domain = I915_GEM_DOMAIN_SAMPLER;
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}
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ss = batch_alloc(batch, sizeof(*ss), 64);
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offset = batch_offset(batch, ss);
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ss->ss0.surface_type = GEN8_SURFACE_2D;
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ss->ss0.surface_format = format;
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ss->ss0.render_cache_read_write = 1;
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ss->ss0.vertical_alignment = 1; /* align 4 */
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ss->ss0.horizontal_alignment = 1; /* align 4 */
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if (buf->tiling == I915_TILING_X)
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ss->ss0.tiled_mode = 2;
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else if (buf->tiling == I915_TILING_Y)
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ss->ss0.tiled_mode = 3;
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ss->ss8.base_addr = buf->bo->offset;
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ret = drm_intel_bo_emit_reloc(batch->bo,
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batch_offset(batch, ss) + 8 * 4,
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buf->bo, 0,
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read_domain, write_domain);
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igt_assert_eq(ret, 0);
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ss->ss2.height = igt_buf_height(buf) - 1;
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ss->ss2.width = igt_buf_width(buf) - 1;
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ss->ss3.pitch = buf->stride - 1;
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ss->ss7.shader_chanel_select_r = 4;
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ss->ss7.shader_chanel_select_g = 5;
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ss->ss7.shader_chanel_select_b = 6;
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ss->ss7.shader_chanel_select_a = 7;
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return offset;
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}
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static uint32_t
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gen7_fill_binding_table(struct intel_batchbuffer *batch,
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struct igt_buf *dst)
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@ -173,6 +238,20 @@ gen7_fill_binding_table(struct intel_batchbuffer *batch,
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return offset;
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}
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static uint32_t
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gen8_fill_binding_table(struct intel_batchbuffer *batch,
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struct igt_buf *dst)
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{
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uint32_t *binding_table, offset;
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binding_table = batch_alloc(batch, 32, 64);
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offset = batch_offset(batch, binding_table);
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binding_table[0] = gen8_fill_surface_state(batch, dst, GEN8_SURFACEFORMAT_R8_UNORM, 1);
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return offset;
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}
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static uint32_t
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gen7_fill_gpgpu_kernel(struct intel_batchbuffer *batch,
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const uint32_t kernel[][4],
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@ -216,6 +295,37 @@ gen7_fill_interface_descriptor(struct intel_batchbuffer *batch, struct igt_buf *
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return offset;
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}
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static uint32_t
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gen8_fill_interface_descriptor(struct intel_batchbuffer *batch, struct igt_buf *dst,
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const uint32_t kernel[][4], size_t size)
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{
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struct gen8_interface_descriptor_data *idd;
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uint32_t offset;
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uint32_t binding_table_offset, kernel_offset;
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binding_table_offset = gen8_fill_binding_table(batch, dst);
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kernel_offset = gen7_fill_gpgpu_kernel(batch, kernel, size);
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idd = batch_alloc(batch, sizeof(*idd), 64);
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offset = batch_offset(batch, idd);
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idd->desc0.kernel_start_pointer = (kernel_offset >> 6);
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idd->desc2.single_program_flow = 1;
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idd->desc2.floating_point_mode = GEN8_FLOATING_POINT_IEEE_754;
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idd->desc3.sampler_count = 0; /* 0 samplers used */
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idd->desc3.sampler_state_pointer = 0;
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idd->desc4.binding_table_entry_count = 0;
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idd->desc4.binding_table_pointer = (binding_table_offset >> 5);
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idd->desc5.constant_urb_entry_read_offset = 0;
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idd->desc5.constant_urb_entry_read_length = 1; /* grf 1 */
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return offset;
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}
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static void
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gen7_emit_state_base_address(struct intel_batchbuffer *batch)
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{
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@ -243,6 +353,42 @@ gen7_emit_state_base_address(struct intel_batchbuffer *batch)
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OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
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}
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static void
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gen8_emit_state_base_address(struct intel_batchbuffer *batch)
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{
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OUT_BATCH(GEN8_STATE_BASE_ADDRESS | (16 - 2));
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/* general */
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OUT_BATCH(0 | (0x78 << 4) | (0 << 1) | BASE_ADDRESS_MODIFY);
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OUT_BATCH(0);
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/* stateless data port */
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OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
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/* surface */
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OUT_RELOC(batch->bo, I915_GEM_DOMAIN_SAMPLER, 0, BASE_ADDRESS_MODIFY);
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/* dynamic */
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OUT_RELOC(batch->bo, I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION,
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0, BASE_ADDRESS_MODIFY);
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/* indirect */
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OUT_BATCH(0);
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OUT_BATCH(0 );
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/* instruction */
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OUT_RELOC(batch->bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
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/* general state buffer size */
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OUT_BATCH(0xfffff000 | 1);
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/* dynamic state buffer size */
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OUT_BATCH(1 << 12 | 1);
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/* indirect object buffer size */
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OUT_BATCH(0xfffff000 | 1);
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/* intruction buffer size, must set modify enable bit, otherwise it may result in GPU hang */
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OUT_BATCH(1 << 12 | 1);
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}
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static void
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gen7_emit_vfe_state_gpgpu(struct intel_batchbuffer *batch)
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{
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@ -268,6 +414,29 @@ gen7_emit_vfe_state_gpgpu(struct intel_batchbuffer *batch)
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OUT_BATCH(0);
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}
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static void
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gen8_emit_vfe_state_gpgpu(struct intel_batchbuffer *batch)
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{
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OUT_BATCH(GEN8_MEDIA_VFE_STATE | (9 - 2));
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/* scratch buffer */
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OUT_BATCH(0);
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OUT_BATCH(0);
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/* number of threads & urb entries */
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OUT_BATCH(1 << 16 | 1 << 8);
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OUT_BATCH(0);
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/* urb entry size & curbe size */
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OUT_BATCH(0 << 16 | 1);
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/* scoreboard */
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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}
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static void
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gen7_emit_curbe_load(struct intel_batchbuffer *batch, uint32_t curbe_buffer)
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{
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@ -290,6 +459,17 @@ gen7_emit_interface_descriptor_load(struct intel_batchbuffer *batch, uint32_t in
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OUT_BATCH(interface_descriptor);
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}
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static void
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gen8_emit_interface_descriptor_load(struct intel_batchbuffer *batch, uint32_t interface_descriptor)
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{
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OUT_BATCH(GEN8_MEDIA_INTERFACE_DESCRIPTOR_LOAD | (4 - 2));
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OUT_BATCH(0);
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/* interface descriptor data length */
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OUT_BATCH(sizeof(struct gen8_interface_descriptor_data));
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/* interface descriptor address, is relative to the dynamics base address */
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OUT_BATCH(interface_descriptor);
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}
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static void
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gen7_emit_gpgpu_walk(struct intel_batchbuffer *batch,
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unsigned x, unsigned y,
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@ -347,6 +527,66 @@ gen7_emit_gpgpu_walk(struct intel_batchbuffer *batch,
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OUT_BATCH(0xffffffff);
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}
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static void
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gen8_emit_gpgpu_walk(struct intel_batchbuffer *batch,
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unsigned x, unsigned y,
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unsigned width, unsigned height)
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{
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uint32_t x_dim, y_dim, tmp, right_mask;
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/*
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* Simply do SIMD16 based dispatch, so every thread uses
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* SIMD16 channels.
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*
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* Define our own thread group size, e.g 16x1 for every group, then
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* will have 1 thread each group in SIMD16 dispatch. So thread
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* width/height/depth are all 1.
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*
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* Then thread group X = width / 16 (aligned to 16)
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* thread group Y = height;
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*/
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x_dim = (width + 15) / 16;
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y_dim = height;
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tmp = width & 15;
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if (tmp == 0)
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right_mask = (1 << 16) - 1;
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else
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right_mask = (1 << tmp) - 1;
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OUT_BATCH(GEN7_GPGPU_WALKER | 13);
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OUT_BATCH(0); /* kernel offset */
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OUT_BATCH(0); /* indirect data length */
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OUT_BATCH(0); /* indirect data offset */
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/* SIMD size, thread w/h/d */
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OUT_BATCH(1 << 30 | /* SIMD16 */
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0 << 16 | /* depth:1 */
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0 << 8 | /* height:1 */
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0); /* width:1 */
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/* thread group X */
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(x_dim);
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/* thread group Y */
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(y_dim);
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/* thread group Z */
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OUT_BATCH(0);
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OUT_BATCH(1);
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/* right mask */
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OUT_BATCH(right_mask);
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/* bottom mask, height 1, always 0xffffffff */
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OUT_BATCH(0xffffffff);
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}
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/*
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* This sets up the gpgpu pipeline,
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*
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@ -403,13 +643,9 @@ gen7_gpgpu_fillfunc(struct intel_batchbuffer *batch,
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OUT_BATCH(GEN7_PIPELINE_SELECT | PIPELINE_SELECT_GPGPU);
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gen7_emit_state_base_address(batch);
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gen7_emit_vfe_state_gpgpu(batch);
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gen7_emit_curbe_load(batch, curbe_buffer);
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gen7_emit_interface_descriptor_load(batch, interface_descriptor);
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gen7_emit_gpgpu_walk(batch, x, y, width, height);
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OUT_BATCH(MI_BATCH_BUFFER_END);
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@ -420,3 +656,51 @@ gen7_gpgpu_fillfunc(struct intel_batchbuffer *batch,
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gen7_render_flush(batch, batch_end);
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intel_batchbuffer_reset(batch);
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}
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void
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gen8_gpgpu_fillfunc(struct intel_batchbuffer *batch,
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struct igt_buf *dst,
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unsigned x, unsigned y,
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unsigned width, unsigned height,
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uint8_t color)
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{
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uint32_t curbe_buffer, interface_descriptor;
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uint32_t batch_end;
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intel_batchbuffer_flush(batch);
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/* setup states */
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batch->ptr = &batch->buffer[BATCH_STATE_SPLIT];
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/*
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* const buffer needs to fill for every thread, but as we have just 1 thread
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* per every group, so need only one curbe data.
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*
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* For each thread, just use thread group ID for buffer offset.
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*/
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curbe_buffer = gen7_fill_curbe_buffer_data(batch, color);
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interface_descriptor = gen8_fill_interface_descriptor(batch, dst,
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gen8_gpgpu_kernel,
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sizeof(gen8_gpgpu_kernel));
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igt_assert(batch->ptr < &batch->buffer[4095]);
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batch->ptr = batch->buffer;
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/* GPGPU pipeline */
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OUT_BATCH(GEN7_PIPELINE_SELECT | PIPELINE_SELECT_GPGPU);
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gen8_emit_state_base_address(batch);
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gen8_emit_vfe_state_gpgpu(batch);
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gen7_emit_curbe_load(batch, curbe_buffer);
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gen8_emit_interface_descriptor_load(batch, interface_descriptor);
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gen8_emit_gpgpu_walk(batch, x, y, width, height);
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OUT_BATCH(MI_BATCH_BUFFER_END);
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batch_end = batch_align(batch, 8);
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igt_assert(batch_end < BATCH_STATE_SPLIT);
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gen7_render_flush(batch, batch_end);
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intel_batchbuffer_reset(batch);
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}
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@ -34,4 +34,11 @@ gen7_gpgpu_fillfunc(struct intel_batchbuffer *batch,
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unsigned width, unsigned height,
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uint8_t color);
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void
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gen8_gpgpu_fillfunc(struct intel_batchbuffer *batch,
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struct igt_buf *dst,
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unsigned x, unsigned y,
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unsigned width, unsigned height,
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uint8_t color);
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#endif /* GPGPU_FILL_H */
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@ -787,6 +787,8 @@ igt_fillfunc_t igt_get_gpgpu_fillfunc(int devid)
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if (IS_GEN7(devid))
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fill = gen7_gpgpu_fillfunc;
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else if (IS_BROADWELL(devid))
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fill = gen8_gpgpu_fillfunc;
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return fill;
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}
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