diff --git a/assembler/src/brw_defines.h b/assembler/src/brw_defines.h
index 594b1252..0eb035dd 100644
--- a/assembler/src/brw_defines.h
+++ b/assembler/src/brw_defines.h
@@ -603,6 +603,8 @@
 #define BRW_OPCODE_MAC        72
 #define BRW_OPCODE_MACH       73
 #define BRW_OPCODE_LZD        74
+#define BRW_OPCODE_FBH        75
+#define BRW_OPCODE_FBL        76
 #define BRW_OPCODE_CBIT       77
 #define BRW_OPCODE_ADDC       78
 #define BRW_OPCODE_SAD2       80
diff --git a/assembler/src/gram.y b/assembler/src/gram.y
index 9f6a0f5b..87e5c0c6 100644
--- a/assembler/src/gram.y
+++ b/assembler/src/gram.y
@@ -115,7 +115,7 @@ void set_direct_src_operand(struct src_operand *src, struct direct_reg *reg,
 %token <integer> MOV FRC RNDU RNDD RNDE RNDZ NOT LZD
 %token <integer> MUL MAC MACH LINE SAD2 SADA2 DP4 DPH DP3 DP2
 %token <integer> AVG ADD SEL AND OR XOR SHR SHL ASR CMP CMPN PLN
-%token <integer> ADDC BFI1 BFREV CBIT F16TO32 F32TO16
+%token <integer> ADDC BFI1 BFREV CBIT F16TO32 F32TO16 FBH FBL
 %token <integer> SEND NOP JMPI IF IFF WHILE ELSE BREAK CONT HALT MSAVE
 %token <integer> PUSH MREST POP WAIT DO ENDIF ILLEGAL
 %token <integer> MATH_INST
@@ -418,7 +418,7 @@ unaryinstruction:
 ;
 
 unaryop:	MOV | FRC | RNDU | RNDD | RNDE | RNDZ | NOT | LZD | BFREV | CBIT
-          | F16TO32 | F32TO16
+          | F16TO32 | F32TO16 | FBH | FBL
 ;
 
 binaryinstruction:
diff --git a/assembler/src/lex.l b/assembler/src/lex.l
index cbc0aa99..cb56915b 100644
--- a/assembler/src/lex.l
+++ b/assembler/src/lex.l
@@ -84,6 +84,8 @@ yylval.integer = BRW_CHANNEL_W;
 "lzd" { yylval.integer = BRW_OPCODE_LZD; return LZD; }
 "f16to32" { yylval.integer = BRW_OPCODE_F16TO32; return F16TO32; }
 "f32to16" { yylval.integer = BRW_OPCODE_F32TO16; return F32TO16; }
+"fbh" { yylval.integer = BRW_OPCODE_FBH; return FBH; }
+"fbl" { yylval.integer = BRW_OPCODE_FBL; return FBL; }
 
 "mad" { yylval.integer = BRW_OPCODE_MAD; return MAD; }
 "lrp" { yylval.integer = BRW_OPCODE_LRP; return LRP; }