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assembler: Store immediate values in reg.dw1.ud

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Another step in pushing the parsing in struct brw_reg.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
This commit is contained in:
Damien Lespiau 2013-01-25 15:48:58 +00:00
parent 103edccd9b
commit 9c72beb701
2 changed files with 11 additions and 11 deletions
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2
assembler/gen4asm.h
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@ -91,7 +91,7 @@ struct regtype {
struct src_operand { struct src_operand {
struct brw_reg reg; struct brw_reg reg;
int default_region; int default_region;
uint32_t imm32; /* set if reg.file == BRW_IMMEDIATE_VALUE or it is expressing a branch offset */ uint32_t imm32; /* set if src_operand is expressing a branch offset */
char *reloc_target; /* bspec: branching instructions JIP and UIP are source operands */ char *reloc_target; /* bspec: branching instructions JIP and UIP are source operands */
} src_operand; } src_operand;

20
assembler/gram.y
View File

@ -1030,7 +1030,7 @@ sendinstruction: predicate SEND execsize exp post_dst payload msgtarget
if ($7.reg.type != BRW_REGISTER_TYPE_UD && if ($7.reg.type != BRW_REGISTER_TYPE_UD &&
$7.reg.type != BRW_REGISTER_TYPE_D && $7.reg.type != BRW_REGISTER_TYPE_D &&
$7.reg.type != BRW_REGISTER_TYPE_V) { $7.reg.type != BRW_REGISTER_TYPE_V) {
fprintf (stderr, "%d: non-int D/UD/V representation: %d,type=%d\n", yylineno, $7.imm32, $7.reg.type); fprintf (stderr, "%d: non-int D/UD/V representation: %d,type=%d\n", yylineno, $7.reg.dw1.ud, $7.reg.type);
YYERROR; YYERROR;
} }
memset(&$$, 0, sizeof($$)); memset(&$$, 0, sizeof($$));
@ -1045,7 +1045,7 @@ sendinstruction: predicate SEND execsize exp post_dst payload msgtarget
YYERROR; YYERROR;
$$.bits1.da1.src1_reg_file = BRW_IMMEDIATE_VALUE; $$.bits1.da1.src1_reg_file = BRW_IMMEDIATE_VALUE;
$$.bits1.da1.src1_reg_type = $7.reg.type; $$.bits1.da1.src1_reg_type = $7.reg.type;
$$.bits3.ud = $7.imm32; $$.bits3.ud = $7.reg.dw1.ud;
} }
| predicate SEND execsize dst sendleadreg sndopr imm32reg instoptions | predicate SEND execsize dst sendleadreg sndopr imm32reg instoptions
{ {
@ -1059,7 +1059,7 @@ sendinstruction: predicate SEND execsize exp post_dst payload msgtarget
if ($7.reg.type != BRW_REGISTER_TYPE_UD && if ($7.reg.type != BRW_REGISTER_TYPE_UD &&
$7.reg.type != BRW_REGISTER_TYPE_D && $7.reg.type != BRW_REGISTER_TYPE_D &&
$7.reg.type != BRW_REGISTER_TYPE_V) { $7.reg.type != BRW_REGISTER_TYPE_V) {
fprintf (stderr, "%d: non-int D/UD/V representation: %d,type=%d\n", yylineno, $7.imm32, $7.reg.type); fprintf (stderr, "%d: non-int D/UD/V representation: %d,type=%d\n", yylineno, $7.reg.dw1.ud, $7.reg.type);
YYERROR; YYERROR;
} }
@ -1089,7 +1089,7 @@ sendinstruction: predicate SEND execsize exp post_dst payload msgtarget
$$.bits1.da1.src1_reg_file = BRW_IMMEDIATE_VALUE; $$.bits1.da1.src1_reg_file = BRW_IMMEDIATE_VALUE;
$$.bits1.da1.src1_reg_type = $7.reg.type; $$.bits1.da1.src1_reg_type = $7.reg.type;
$$.bits3.ud = $7.imm32; $$.bits3.ud = $7.reg.dw1.ud;
$$.bits3.generic_gen5.end_of_thread = !!($6 & EX_DESC_EOT_MASK); $$.bits3.generic_gen5.end_of_thread = !!($6 & EX_DESC_EOT_MASK);
} }
| predicate SEND execsize dst sendleadreg sndopr directsrcoperand instoptions | predicate SEND execsize dst sendleadreg sndopr directsrcoperand instoptions
@ -1141,7 +1141,7 @@ sendinstruction: predicate SEND execsize exp post_dst payload msgtarget
if ($8.reg.type != BRW_REGISTER_TYPE_UD && if ($8.reg.type != BRW_REGISTER_TYPE_UD &&
$8.reg.type != BRW_REGISTER_TYPE_D && $8.reg.type != BRW_REGISTER_TYPE_D &&
$8.reg.type != BRW_REGISTER_TYPE_V) { $8.reg.type != BRW_REGISTER_TYPE_V) {
fprintf (stderr, "%d: non-int D/UD/V representation: %d,type=%d\n", yylineno, $8.imm32, $8.reg.type); fprintf (stderr, "%d: non-int D/UD/V representation: %d,type=%d\n", yylineno, $8.reg.dw1.ud, $8.reg.type);
YYERROR; YYERROR;
} }
memset(&$$, 0, sizeof($$)); memset(&$$, 0, sizeof($$));
@ -1158,11 +1158,11 @@ sendinstruction: predicate SEND execsize exp post_dst payload msgtarget
$$.bits1.da1.src1_reg_type = $8.reg.type; $$.bits1.da1.src1_reg_type = $8.reg.type;
if (IS_GENx(5)) { if (IS_GENx(5)) {
$$.bits2.send_gen5.sfid = ($7 & EX_DESC_SFID_MASK); $$.bits2.send_gen5.sfid = ($7 & EX_DESC_SFID_MASK);
$$.bits3.ud = $8.imm32; $$.bits3.ud = $8.reg.dw1.ud;
$$.bits3.generic_gen5.end_of_thread = !!($7 & EX_DESC_EOT_MASK); $$.bits3.generic_gen5.end_of_thread = !!($7 & EX_DESC_EOT_MASK);
} }
else else
$$.bits3.ud = $8.imm32; $$.bits3.ud = $8.reg.dw1.ud;
} }
| predicate SEND execsize dst sendleadreg payload exp directsrcoperand instoptions | predicate SEND execsize dst sendleadreg payload exp directsrcoperand instoptions
{ {
@ -1837,7 +1837,7 @@ imm32reg: imm32 srcimmtype
memset (&$$, '\0', sizeof ($$)); memset (&$$, '\0', sizeof ($$));
$$.reg.file = BRW_IMMEDIATE_VALUE; $$.reg.file = BRW_IMMEDIATE_VALUE;
$$.reg.type = $2; $$.reg.type = $2;
$$.imm32 = d; $$.reg.dw1.ud = d;
} }
; ;
@ -2869,7 +2869,7 @@ int set_instruction_src0(struct brw_instruction *instr,
instr->bits1.da1.src0_reg_file = src->reg.file; instr->bits1.da1.src0_reg_file = src->reg.file;
instr->bits1.da1.src0_reg_type = src->reg.type; instr->bits1.da1.src0_reg_type = src->reg.type;
if (src->reg.file == BRW_IMMEDIATE_VALUE) { if (src->reg.file == BRW_IMMEDIATE_VALUE) {
instr->bits3.ud = src->imm32; instr->bits3.ud = src->reg.dw1.ud;
} else if (src->reg.address_mode == BRW_ADDRESS_DIRECT) { } else if (src->reg.address_mode == BRW_ADDRESS_DIRECT) {
if (instr->header.access_mode == BRW_ALIGN_1) { if (instr->header.access_mode == BRW_ALIGN_1) {
instr->bits2.da1.src0_subreg_nr = get_subreg_address(src->reg.file, src->reg.type, src->reg.subnr, src->reg.address_mode); instr->bits2.da1.src0_subreg_nr = get_subreg_address(src->reg.file, src->reg.type, src->reg.subnr, src->reg.address_mode);
@ -2933,7 +2933,7 @@ int set_instruction_src1(struct brw_instruction *instr,
instr->bits1.da1.src1_reg_file = src->reg.file; instr->bits1.da1.src1_reg_file = src->reg.file;
instr->bits1.da1.src1_reg_type = src->reg.type; instr->bits1.da1.src1_reg_type = src->reg.type;
if (src->reg.file == BRW_IMMEDIATE_VALUE) { if (src->reg.file == BRW_IMMEDIATE_VALUE) {
instr->bits3.ud = src->imm32; instr->bits3.ud = src->reg.dw1.ud;
} else if (src->reg.address_mode == BRW_ADDRESS_DIRECT) { } else if (src->reg.address_mode == BRW_ADDRESS_DIRECT) {
if (instr->header.access_mode == BRW_ALIGN_1) { if (instr->header.access_mode == BRW_ALIGN_1) {
instr->bits3.da1.src1_subreg_nr = get_subreg_address(src->reg.file, src->reg.type, src->reg.subnr, src->reg.address_mode); instr->bits3.da1.src1_subreg_nr = get_subreg_address(src->reg.file, src->reg.type, src->reg.subnr, src->reg.address_mode);