mirror of
https://github.com/tiagovignatti/intel-gpu-tools.git
synced 2026-08-20 12:52:55 +00:00
assembler: Move struct relocation out of relocatable instructions
Now that all instructions (relocatable or not) are struct brw_program_instructions, this means we can move the relocation specific information out the "relocatable instruction" structure. This will allow us to share the relocation information between different types of instructions. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
This commit is contained in:
+39
-37
@@ -208,14 +208,16 @@ brw_program_add_instruction(struct brw_program *p,
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brw_program_append_entry(p, list_entry);
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}
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static void brw_program_add_relocatable(struct brw_program *p,
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struct brw_program_instruction *reloc)
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static void
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brw_program_add_relocatable(struct brw_program *p,
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struct brw_program_instruction *instruction)
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{
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struct brw_program_instruction *list_entry;
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list_entry = calloc(sizeof(struct brw_program_instruction), 1);
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list_entry->type = GEN4ASM_INSTRUCTION_GEN_RELOCATABLE;
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list_entry->insn.reloc = reloc->insn.reloc;
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list_entry->insn.gen = instruction->insn.gen;
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list_entry->reloc = instruction->reloc;
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brw_program_append_entry(p, list_entry);
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}
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@@ -724,8 +726,8 @@ ifelseinstruction: ENDIF
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memset(&$$, 0, sizeof($$));
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GEN(&$$)->header.opcode = $1;
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GEN(&$$)->header.execution_size = $2;
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$$.insn.reloc.first_reloc_target = $3.reloc_target;
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$$.insn.reloc.first_reloc_offset = $3.imm32;
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$$.reloc.first_reloc_target = $3.reloc_target;
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$$.reloc.first_reloc_offset = $3.imm32;
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}
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| ELSE execsize relativelocation instoptions
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{
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@@ -741,14 +743,14 @@ ifelseinstruction: ENDIF
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set_instruction_dest(&$$, &ip_dst);
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set_instruction_src0(&$$, &ip_src, NULL);
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set_instruction_src1(&$$, &$3, NULL);
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$$.insn.reloc.first_reloc_target = $3.reloc_target;
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$$.insn.reloc.first_reloc_offset = $3.imm32;
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$$.reloc.first_reloc_target = $3.reloc_target;
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$$.reloc.first_reloc_offset = $3.imm32;
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} else if(IS_GENp(6)) {
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memset(&$$, 0, sizeof($$));
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GEN(&$$)->header.opcode = $1;
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GEN(&$$)->header.execution_size = $2;
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$$.insn.reloc.first_reloc_target = $3.reloc_target;
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$$.insn.reloc.first_reloc_offset = $3.imm32;
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$$.reloc.first_reloc_target = $3.reloc_target;
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$$.reloc.first_reloc_offset = $3.imm32;
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} else {
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error(&@1, "'ELSE' instruction is not implemented.\n");
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}
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@@ -773,8 +775,8 @@ ifelseinstruction: ENDIF
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set_instruction_src0(&$$, &ip_src, NULL);
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set_instruction_src1(&$$, &$4, NULL);
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}
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$$.insn.reloc.first_reloc_target = $4.reloc_target;
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$$.insn.reloc.first_reloc_offset = $4.imm32;
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$$.reloc.first_reloc_target = $4.reloc_target;
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$$.reloc.first_reloc_offset = $4.imm32;
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}
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| predicate IF execsize relativelocation relativelocation
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{
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@@ -786,10 +788,10 @@ ifelseinstruction: ENDIF
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set_instruction_predicate(&$$, &$1);
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GEN(&$$)->header.opcode = $2;
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GEN(&$$)->header.execution_size = $3;
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$$.insn.reloc.first_reloc_target = $4.reloc_target;
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$$.insn.reloc.first_reloc_offset = $4.imm32;
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$$.insn.reloc.second_reloc_target = $5.reloc_target;
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$$.insn.reloc.second_reloc_offset = $5.imm32;
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$$.reloc.first_reloc_target = $4.reloc_target;
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$$.reloc.first_reloc_offset = $4.imm32;
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$$.reloc.second_reloc_target = $5.reloc_target;
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$$.reloc.second_reloc_offset = $5.imm32;
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}
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;
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@@ -809,8 +811,8 @@ loopinstruction: predicate WHILE execsize relativelocation instoptions
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GEN(&$$)->header.thread_control |= BRW_THREAD_SWITCH;
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set_instruction_src0(&$$, &ip_src, NULL);
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set_instruction_src1(&$$, &$4, NULL);
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$$.insn.reloc.first_reloc_target = $4.reloc_target;
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$$.insn.reloc.first_reloc_offset = $4.imm32;
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$$.reloc.first_reloc_target = $4.reloc_target;
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$$.reloc.first_reloc_offset = $4.imm32;
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} else if (IS_GENp(6)) {
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/* Gen6 spec:
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dest must have the same element size as src0.
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@@ -819,8 +821,8 @@ loopinstruction: predicate WHILE execsize relativelocation instoptions
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set_instruction_predicate(&$$, &$1);
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GEN(&$$)->header.opcode = $2;
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GEN(&$$)->header.execution_size = $3;
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$$.insn.reloc.first_reloc_target = $4.reloc_target;
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$$.insn.reloc.first_reloc_offset = $4.imm32;
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$$.reloc.first_reloc_target = $4.reloc_target;
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$$.reloc.first_reloc_offset = $4.imm32;
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} else {
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error(&@2, "'WHILE' instruction is not implemented!\n");
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}
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@@ -839,10 +841,10 @@ haltinstruction: predicate HALT execsize relativelocation relativelocation insto
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memset(&$$, 0, sizeof($$));
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set_instruction_predicate(&$$, &$1);
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GEN(&$$)->header.opcode = $2;
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$$.insn.reloc.first_reloc_target = $4.reloc_target;
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$$.insn.reloc.first_reloc_offset = $4.imm32;
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$$.insn.reloc.second_reloc_target = $5.reloc_target;
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$$.insn.reloc.second_reloc_offset = $5.imm32;
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$$.reloc.first_reloc_target = $4.reloc_target;
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$$.reloc.first_reloc_offset = $4.imm32;
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$$.reloc.second_reloc_target = $5.reloc_target;
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$$.reloc.second_reloc_offset = $5.imm32;
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dst_null_reg.width = $3;
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set_instruction_dest(&$$, &dst_null_reg);
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set_instruction_src0(&$$, &src_null_reg, NULL);
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@@ -856,8 +858,8 @@ multibranchinstruction:
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set_instruction_predicate(&$$, &$1);
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GEN(&$$)->header.opcode = $2;
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GEN(&$$)->header.thread_control |= BRW_THREAD_SWITCH;
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$$.insn.reloc.first_reloc_target = $4.reloc_target;
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$$.insn.reloc.first_reloc_offset = $4.imm32;
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$$.reloc.first_reloc_target = $4.reloc_target;
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$$.reloc.first_reloc_offset = $4.imm32;
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dst_null_reg.width = $3;
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set_instruction_dest(&$$, &dst_null_reg);
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}
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@@ -868,10 +870,10 @@ multibranchinstruction:
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set_instruction_predicate(&$$, &$1);
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GEN(&$$)->header.opcode = $2;
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GEN(&$$)->header.thread_control |= BRW_THREAD_SWITCH;
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$$.insn.reloc.first_reloc_target = $4.reloc_target;
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$$.insn.reloc.first_reloc_offset = $4.imm32;
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$$.insn.reloc.second_reloc_target = $5.reloc_target;
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$$.insn.reloc.second_reloc_offset = $5.imm32;
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$$.reloc.first_reloc_target = $4.reloc_target;
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$$.reloc.first_reloc_offset = $4.imm32;
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$$.reloc.second_reloc_target = $5.reloc_target;
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$$.reloc.second_reloc_offset = $5.imm32;
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dst_null_reg.width = $3;
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set_instruction_dest(&$$, &dst_null_reg);
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set_instruction_src0(&$$, &src_null_reg, NULL);
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@@ -912,8 +914,8 @@ subroutineinstruction:
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src0.reg.vstride = 2; /*encoded 2*/
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set_instruction_src0(&$$, &src0, NULL);
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$$.insn.reloc.first_reloc_target = $5.reloc_target;
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$$.insn.reloc.first_reloc_offset = $5.imm32;
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$$.reloc.first_reloc_target = $5.reloc_target;
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$$.reloc.first_reloc_offset = $5.imm32;
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}
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| predicate RET execsize dstoperandex src instoptions
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{
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@@ -1359,8 +1361,8 @@ jumpinstruction: predicate JMPI execsize relativelocation2
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set_instruction_dest(&$$, &ip_dst);
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set_instruction_src0(&$$, &ip_src, NULL);
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set_instruction_src1(&$$, &$4, NULL);
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$$.insn.reloc.first_reloc_target = $4.reloc_target;
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$$.insn.reloc.first_reloc_offset = $4.imm32;
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$$.reloc.first_reloc_target = $4.reloc_target;
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$$.reloc.first_reloc_offset = $4.imm32;
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}
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;
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@@ -1388,10 +1390,10 @@ breakinstruction: predicate breakop execsize relativelocation relativelocation i
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set_instruction_predicate(&$$, &$1);
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GEN(&$$)->header.opcode = $2;
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GEN(&$$)->header.execution_size = $3;
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$$.insn.reloc.first_reloc_target = $4.reloc_target;
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$$.insn.reloc.first_reloc_offset = $4.imm32;
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$$.insn.reloc.second_reloc_target = $5.reloc_target;
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$$.insn.reloc.second_reloc_offset = $5.imm32;
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$$.reloc.first_reloc_target = $4.reloc_target;
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$$.reloc.first_reloc_offset = $4.imm32;
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$$.reloc.second_reloc_target = $5.reloc_target;
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$$.reloc.second_reloc_offset = $5.imm32;
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}
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;
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