mirror of
https://github.com/tiagovignatti/intel-gpu-tools.git
synced 2026-08-21 13:23:02 +00:00
Prepare for 64bit relocation addresses
This reveal that quite a few locations were writing relocation offsets but only allowing for 32 bit addresses. To reveal such places in active tests, we also now double check that we do not use more batch space than declared. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
@@ -87,10 +87,9 @@ store_pipe_control_loop(bool preuse_buffer)
|
||||
* different domain than what the pipe control write
|
||||
* (and kernel wa) uses!
|
||||
*/
|
||||
OUT_RELOC(target_bo,
|
||||
OUT_RELOC_FENCED(target_bo,
|
||||
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
|
||||
0);
|
||||
BLIT_RELOC_UDW(devid);
|
||||
OUT_BATCH(0xdeadbeef);
|
||||
ADVANCE_BATCH();
|
||||
|
||||
@@ -104,10 +103,9 @@ store_pipe_control_loop(bool preuse_buffer)
|
||||
BEGIN_BATCH(5);
|
||||
OUT_BATCH(GFX_OP_PIPE_CONTROL + 1);
|
||||
OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);
|
||||
OUT_RELOC(target_bo,
|
||||
OUT_RELOC_FENCED(target_bo,
|
||||
I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
|
||||
PIPE_CONTROL_GLOBAL_GTT);
|
||||
BLIT_RELOC_UDW(devid);
|
||||
OUT_BATCH(val); /* write data */
|
||||
ADVANCE_BATCH();
|
||||
|
||||
|
||||
Reference in New Issue
Block a user