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https://github.com/tiagovignatti/intel-gpu-tools.git
synced 2026-08-19 04:13:01 +00:00
Prepare for 64bit relocation addresses
This reveal that quite a few locations were writing relocation offsets but only allowing for 32 bit addresses. To reveal such places in active tests, we also now double check that we do not use more batch space than declared. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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+6
-14
@@ -17,7 +17,7 @@ struct intel_batchbuffer {
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drm_intel_bo *bo;
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uint8_t buffer[BATCH_SZ];
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uint8_t *ptr;
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uint8_t *ptr, *end;
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uint8_t *state;
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};
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@@ -39,7 +39,7 @@ void intel_batchbuffer_data(struct intel_batchbuffer *batch,
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void intel_batchbuffer_emit_reloc(struct intel_batchbuffer *batch,
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drm_intel_bo *buffer,
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uint32_t delta,
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uint64_t delta,
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uint32_t read_domains,
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uint32_t write_domain,
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int fenced);
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@@ -85,7 +85,9 @@ intel_batchbuffer_require_space(struct intel_batchbuffer *batch,
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* scope.
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*/
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#define BEGIN_BATCH(n) do { \
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igt_assert(batch->end == NULL); \
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intel_batchbuffer_require_space(batch, (n)*4); \
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batch->end = batch->ptr + (n) * 4; \
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} while (0)
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/**
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@@ -144,6 +146,8 @@ intel_batchbuffer_require_space(struct intel_batchbuffer *batch,
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* scope.
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*/
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#define ADVANCE_BATCH() do { \
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igt_assert(batch->ptr == batch->end); \
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batch->end = NULL; \
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} while(0)
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#define BLIT_COPY_BATCH_START(devid, flags) do { \
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@@ -177,18 +181,6 @@ intel_batchbuffer_require_space(struct intel_batchbuffer *batch,
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} \
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} while(0)
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/**
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* BLIT_RELOC_UDW:
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* @devid: pci device id of the drm device
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*
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* Emits the upper relocation DWORD on gen8+ and nothing on earlier generations.
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*/
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#define BLIT_RELOC_UDW(devid) do { \
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if (intel_gen(devid) >= 8) { \
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OUT_BATCH(0); \
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} \
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} while(0)
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void
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intel_blt_copy(struct intel_batchbuffer *batch,
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drm_intel_bo *src_bo, int src_x1, int src_y1, int src_pitch,
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