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Code Issues Releases Wiki Activity

Prepare for 64bit relocation addresses

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This reveal that quite a few locations were writing relocation offsets
but only allowing for 32 bit addresses. To reveal such places in active
tests, we also now double check that we do not use more batch space than
declared.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Chris Wilson
2014-08-29 15:19:57 +01:00
parent 86055df968
commit 982f7eb238
34 changed files with 47 additions and 109 deletions
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benchmarks/intel_upload_blit_large.c
-2
View File
@@ -104,11 +104,9 @@ do_render(drm_intel_bufmgr *bufmgr, struct intel_batchbuffer *batch,
OUT_BATCH(0); /* dst x1,y1 */
OUT_BATCH((height << 16) | width); /* dst x2,y2 */
OUT_RELOC(dst_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
BLIT_RELOC_UDW(batch->devid);
OUT_BATCH(0); /* src x1,y1 */
OUT_BATCH(width * 4); /* src pitch */
OUT_RELOC(src_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
BLIT_RELOC_UDW(batch->devid);
ADVANCE_BATCH();
intel_batchbuffer_flush(batch);
benchmarks/intel_upload_blit_large_gtt.c
-2
View File
@@ -102,11 +102,9 @@ do_render(drm_intel_bufmgr *bufmgr, struct intel_batchbuffer *batch,
OUT_BATCH(0); /* dst x1,y1 */
OUT_BATCH((height << 16) | width); /* dst x2,y2 */
OUT_RELOC(dst_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
BLIT_RELOC_UDW(batch->devid);
OUT_BATCH(0); /* src x1,y1 */
OUT_BATCH(width * 4); /* src pitch */
OUT_RELOC(src_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
BLIT_RELOC_UDW(batch->devid);
ADVANCE_BATCH();
intel_batchbuffer_flush(batch);
benchmarks/intel_upload_blit_large_map.c
-2
View File
@@ -105,11 +105,9 @@ do_render(drm_intel_bufmgr *bufmgr, struct intel_batchbuffer *batch,
OUT_BATCH(0); /* dst x1,y1 */
OUT_BATCH((height << 16) | width); /* dst x2,y2 */
OUT_RELOC(dst_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
BLIT_RELOC_UDW(batch->devid);
OUT_BATCH(0); /* src x1,y1 */
OUT_BATCH(width * 4); /* src pitch */
OUT_RELOC(src_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
BLIT_RELOC_UDW(batch->devid);
ADVANCE_BATCH();
intel_batchbuffer_flush(batch);
benchmarks/intel_upload_blit_small.c
-2
View File
@@ -115,11 +115,9 @@ do_render(drm_intel_bufmgr *bufmgr, struct intel_batchbuffer *batch,
OUT_BATCH(0); /* dst x1,y1 */
OUT_BATCH((height << 16) | width); /* dst x2,y2 */
OUT_RELOC(dst_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
BLIT_RELOC_UDW(batch->devid);
OUT_BATCH(0); /* src x1,y1 */
OUT_BATCH(width * 4); /* src pitch */
OUT_RELOC(src_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
BLIT_RELOC_UDW(batch->devid);
ADVANCE_BATCH();
intel_batchbuffer_flush(batch);