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skl_compute_wrpll: Make sure we respect the DCO frequency constraints
We might as well verify that we have a semblance of all being in order by making sure the DCO frequency is within the expected bounds. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
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@ -60,6 +60,10 @@ struct skl_wrpll_params {
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uint32_t kdiv;
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uint32_t pdiv;
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uint32_t central_freq;
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/* for this test code only */
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uint64_t central_freq_hz;
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unsigned int p0, p1, p2;
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};
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static bool
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@ -239,6 +243,12 @@ found:
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}
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/* for this unit test only */
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wrpll_params->central_freq_hz = dco_central_freq[min_dco_index];
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wrpll_params->p0 = candidate_p0[min_dco_index];
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wrpll_params->p1 = candidate_p1[min_dco_index];
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wrpll_params->p2 = candidate_p2[min_dco_index];
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return true;
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}
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@ -406,6 +416,7 @@ skl_ddi_calculate_wrpll2(int clock /* in Hz */,
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};
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struct skl_wrpll_context ctx;
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unsigned int dco, d, i;
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unsigned int p0, p1, p2;
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skl_wrpll_context_init(&ctx);
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@ -428,6 +439,12 @@ skl_ddi_calculate_wrpll2(int clock /* in Hz */,
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skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2);
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/* for this unit test only */
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wrpll_params->central_freq_hz = ctx.central_freq;
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wrpll_params->p0 = p0;
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wrpll_params->p1 = p1;
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wrpll_params->p2 = p2;
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return true;
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}
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@ -829,6 +846,31 @@ static void test_run(struct test_ops *test)
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clock);
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continue;
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}
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/*
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* make sure we respect the +1%/-6% contraint around the
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* central frequency
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*/
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{
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unsigned int p = params.p0 * params.p1 * params.p2;
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uint64_t dco_freq = (uint64_t)p * clock * 5;
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uint64_t central_freq = params.central_freq_hz;
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uint64_t deviation;
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uint64_t diff;
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diff = abs_diff(dco_freq, central_freq);
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deviation = div64_u64(10000 * diff, central_freq);
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if (dco_freq > central_freq) {
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if (deviation > 100)
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printf("failed constraint for %dHz "
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"deviation=%"PRIu64"\n", clock,
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deviation);
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} else if (deviation > 600)
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printf("failed constraint for %dHz "
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"deviation=%"PRIu64"\n", clock,
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deviation);
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}
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}
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}
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