test/gem_mocs_settings: Testing MOCS register settings

The MOCS registers were added in Gen9 and define the caching policy.
The registers are split into two sets. The first set controls the
EDRAM policy and have a set for each engine, the second set controls
the L3 policy. The two sets use the same index.

The RCS registers and the L3CC registers are stored in the RCS context.

The test checks that the registers are correct by checking the values by
directly reading them via MMIO, then again it tests them by reading them
from within a batch buffer. RCS engine is tested last as it programs the
registers via a batch buffer and this will invalidate the test for
workloads that don't use the render ring or don't run a render batch
first.

v2: Reorganised the structure.
    Added more tests. (Chris Wilson)
v3: Fixed a few bugs. (Chris Wilson)
v4: More Tidy-ups.    (Chris Wilson)
    SKL does does not have a snoop bit. (Peter Antoine)

Signed-off-by: Peter Antoine <peter.antoine@intel.com>

lib/ioctl_wrappers.c

@@ -1401,6 +1401,30 @@ void gem_require_ring(int fd, unsigned ring)
 	igt_require(gem_has_ring(fd, ring));
 }
 
+/**
+ * gem_has_mocs_registers:
+ * @fd: open i915 drm file descriptor
+ *
+ * Feature test macro to query whether the device has MOCS registers.
+ * These exist gen 9+.
+ */
+bool gem_has_mocs_registers(int fd)
+{
+	return intel_gen(intel_get_drm_devid(fd)) >= 9;
+}
+
+/**
+ * gem_require_mocs_registers:
+ * @fd: open i915 drm file descriptor
+ *
+ * Feature test macro to query whether the device has MOCS registers.
+ * These exist gen 9+.
+ */
+void gem_require_mocs_registers(int fd)
+{
+	igt_require(gem_has_mocs_registers(fd));
+}
+
 /* prime */
 
 /**

lib/ioctl_wrappers.h

@@ -154,6 +154,8 @@ bool gem_has_softpin(int fd);
 void gem_require_caching(int fd);
 bool gem_has_ring(int fd, unsigned ring);
 void gem_require_ring(int fd, unsigned ring);
+bool gem_has_mocs_registers(int fd);
+void gem_require_mocs_registers(int fd);
 
 /* prime */
 struct local_dma_buf_sync {