mirror of
				https://github.com/tiagovignatti/intel-gpu-tools.git
				synced 2025-11-04 12:07:12 +00:00 
			
		
		
		
	lib: Enable clflush for 32bit x86 builds
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
		
							parent
							
								
									89f354e0a5
								
							
						
					
					
						commit
						7d08913aeb
					
				
							
								
								
									
										23
									
								
								lib/igt_gt.c
									
									
									
									
									
								
							
							
						
						
									
										23
									
								
								lib/igt_gt.c
									
									
									
									
									
								
							@ -370,6 +370,7 @@ int igt_open_forcewake_handle(void)
 | 
				
			|||||||
}
 | 
					}
 | 
				
			||||||
static unsigned int clflush_size;
 | 
					static unsigned int clflush_size;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					#if defined(__x86_64__) || defined(__i386__)
 | 
				
			||||||
int igt_setup_clflush(void)
 | 
					int igt_setup_clflush(void)
 | 
				
			||||||
{
 | 
					{
 | 
				
			||||||
	FILE *file;
 | 
						FILE *file;
 | 
				
			||||||
@ -378,11 +379,6 @@ int igt_setup_clflush(void)
 | 
				
			|||||||
	int first_stanza = 1;
 | 
						int first_stanza = 1;
 | 
				
			||||||
	int has_clflush = 0;
 | 
						int has_clflush = 0;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
#if !defined(__x86_64__) && !defined(__SSE2__)
 | 
					 | 
				
			||||||
	/* requires mfence + clflush, both SSE2 instructions */
 | 
					 | 
				
			||||||
	return 0;
 | 
					 | 
				
			||||||
#endif
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
	if (clflush_size)
 | 
						if (clflush_size)
 | 
				
			||||||
		return 1;
 | 
							return 1;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
@ -414,9 +410,9 @@ int igt_setup_clflush(void)
 | 
				
			|||||||
	return has_clflush && clflush_size;
 | 
						return has_clflush && clflush_size;
 | 
				
			||||||
}
 | 
					}
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					__attribute__((target("sse2")))
 | 
				
			||||||
void igt_clflush_range(void *addr, int size)
 | 
					void igt_clflush_range(void *addr, int size)
 | 
				
			||||||
{
 | 
					{
 | 
				
			||||||
#if defined(__x86_64__) || defined(__SSE2__)
 | 
					 | 
				
			||||||
	char *p, *end;
 | 
						char *p, *end;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
	end = (char *)addr + size;
 | 
						end = (char *)addr + size;
 | 
				
			||||||
@ -427,10 +423,19 @@ void igt_clflush_range(void *addr, int size)
 | 
				
			|||||||
		__builtin_ia32_clflush(p);
 | 
							__builtin_ia32_clflush(p);
 | 
				
			||||||
	__builtin_ia32_clflush(end - 1); /* magic serialisation for byt+ */
 | 
						__builtin_ia32_clflush(end - 1); /* magic serialisation for byt+ */
 | 
				
			||||||
	__builtin_ia32_mfence();
 | 
						__builtin_ia32_mfence();
 | 
				
			||||||
#else
 | 
					 | 
				
			||||||
	fprintf(stderr, "igt_clflush_range() unsupported\n");
 | 
					 | 
				
			||||||
#endif
 | 
					 | 
				
			||||||
}
 | 
					}
 | 
				
			||||||
 | 
					#else
 | 
				
			||||||
 | 
					int igt_setup_clflush(void)
 | 
				
			||||||
 | 
					{
 | 
				
			||||||
 | 
						/* requires mfence + clflush, both SSE2 instructions */
 | 
				
			||||||
 | 
						return 0;
 | 
				
			||||||
 | 
					}
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					void igt_clflush_range(void *addr, int size)
 | 
				
			||||||
 | 
					{
 | 
				
			||||||
 | 
						fprintf(stderr, "igt_clflush_range() unsupported\n");
 | 
				
			||||||
 | 
					}
 | 
				
			||||||
 | 
					#endif
 | 
				
			||||||
 | 
					
 | 
				
			||||||
/**
 | 
					/**
 | 
				
			||||||
 * intel_detect_and_clear_missed_irq:
 | 
					 * intel_detect_and_clear_missed_irq:
 | 
				
			||||||
 | 
				
			|||||||
		Loading…
	
	
			
			x
			
			
		
	
		Reference in New Issue
	
	Block a user