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https://github.com/tiagovignatti/intel-gpu-tools.git
synced 2025-06-09 17:06:14 +00:00
tests/prime_nv_pcopy: Use asserts in nv_bo_alloc
Step one to untangle the control flow in this test and replace it all with igt assert magic. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
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d502ae6f77
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782cda17b9
@ -56,13 +56,12 @@ typedef struct {
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uint32_t pitch, lines;
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uint32_t pitch, lines;
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} rect;
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} rect;
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static int nv_bo_alloc(struct nouveau_bo **bo, rect *r,
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static void nv_bo_alloc(struct nouveau_bo **bo, rect *r,
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uint32_t w, uint32_t h, uint32_t tile_mode,
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uint32_t w, uint32_t h, uint32_t tile_mode,
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int handle, uint32_t dom)
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int handle, uint32_t dom)
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{
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{
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uint32_t size;
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uint32_t size;
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uint32_t dx = 1, dy = 1, memtype = 0;
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uint32_t dx = 1, dy = 1, memtype = 0;
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int ret;
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*bo = NULL;
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*bo = NULL;
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if (tile_mode) {
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if (tile_mode) {
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@ -104,15 +103,8 @@ static int nv_bo_alloc(struct nouveau_bo **bo, rect *r,
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cfg.nv50.tile_mode = tile_mode;
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cfg.nv50.tile_mode = tile_mode;
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if (dom == NOUVEAU_BO_GART)
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if (dom == NOUVEAU_BO_GART)
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dom |= NOUVEAU_BO_MAP;
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dom |= NOUVEAU_BO_MAP;
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ret = nouveau_bo_new(ndev, dom, 4096, size, &cfg, bo);
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igt_assert(nouveau_bo_new(ndev, dom, 4096, size, &cfg, bo) == 0);
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if (!ret)
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igt_assert(nouveau_bo_map(*bo, NOUVEAU_BO_RDWR, nclient) == 0);
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ret = nouveau_bo_map(*bo, NOUVEAU_BO_RDWR, nclient);
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if (ret) {
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fprintf(stderr, "creating bo failed with %i %s\n",
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ret, strerror(-ret));
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nouveau_bo_ref(NULL, bo);
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return ret;
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}
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igt_debug("new flags %08x memtype %08x tile %08x\n",
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igt_debug("new flags %08x memtype %08x tile %08x\n",
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(*bo)->flags, (*bo)->config.nv50.memtype,
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(*bo)->flags, (*bo)->config.nv50.memtype,
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@ -124,19 +116,11 @@ static int nv_bo_alloc(struct nouveau_bo **bo, rect *r,
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(*bo)->config.nv50.tile_mode = tile_mode;
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(*bo)->config.nv50.tile_mode = tile_mode;
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}
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}
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} else {
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} else {
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ret = nouveau_bo_prime_handle_ref(ndev, handle, bo);
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igt_assert(nouveau_bo_prime_handle_ref(ndev, handle, bo) == 0);
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close(handle);
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close(handle);
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if (ret < 0) {
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igt_assert_f((*bo)->size >= size,
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fprintf(stderr, "receiving bo failed with %i %s\n",
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"expected bo size to be at least %u,"
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ret, strerror(-ret));
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"but received %"PRIu64"\n", size, (*bo)->size);
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return ret;
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}
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if ((*bo)->size < size) {
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fprintf(stderr, "expected bo size to be at least %u,"
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"but received %"PRIu64"\n", size, (*bo)->size);
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nouveau_bo_ref(NULL, bo);
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return -1;
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}
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igt_debug("prime flags %08x memtype %08x tile %08x\n",
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igt_debug("prime flags %08x memtype %08x tile %08x\n",
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(*bo)->flags, (*bo)->config.nv50.memtype,
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(*bo)->flags, (*bo)->config.nv50.memtype,
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(*bo)->config.nv50.tile_mode);
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(*bo)->config.nv50.tile_mode);
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@ -144,8 +128,6 @@ static int nv_bo_alloc(struct nouveau_bo **bo, rect *r,
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(*bo)->config.nv50.tile_mode = tile_mode;
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(*bo)->config.nv50.tile_mode = tile_mode;
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}
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}
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igt_debug("size: %"PRIu64"\n", (*bo)->size);
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igt_debug("size: %"PRIu64"\n", (*bo)->size);
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return ret;
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}
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}
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static inline void
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static inline void
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@ -655,11 +637,8 @@ static int test1_macro(void)
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uint8_t *ptr;
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uint8_t *ptr;
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uint32_t w = 2 * 128, h = 2 * 32, x, y;
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uint32_t w = 2 * 128, h = 2 * 32, x, y;
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ret = nv_bo_alloc(&nvbi, &src, w, h, 0, -1, NOUVEAU_BO_GART);
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nv_bo_alloc(&nvbi, &src, w, h, 0, -1, NOUVEAU_BO_GART);
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if (ret >= 0)
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nv_bo_alloc(&nvbo, &dst, w, h, tile_intel_y, -1, NOUVEAU_BO_GART);
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ret = nv_bo_alloc(&nvbo, &dst, w, h, tile_intel_y, -1, NOUVEAU_BO_GART);
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if (ret < 0)
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goto out;
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nouveau_bo_set_prime(nvbo, &prime_fd);
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nouveau_bo_set_prime(nvbo, &prime_fd);
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@ -699,7 +678,6 @@ static int test1_macro(void)
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if (!ret)
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if (!ret)
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ret = check1_macro(nvbo->map, w/128, h/32);
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ret = check1_macro(nvbo->map, w/128, h/32);
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out:
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nouveau_bo_ref(NULL, &nvbo);
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nouveau_bo_ref(NULL, &nvbo);
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nouveau_bo_ref(NULL, &nvbi);
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nouveau_bo_ref(NULL, &nvbi);
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close(prime_fd);
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close(prime_fd);
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@ -774,13 +752,9 @@ static int test1_micro(void)
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}
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}
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noop_intel(test_intel_bo);
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noop_intel(test_intel_bo);
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ret = nv_bo_alloc(&bo_intel, &intel, w, h, tile_intel_y, prime_fd, 0);
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nv_bo_alloc(&bo_intel, &intel, w, h, tile_intel_y, prime_fd, 0);
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if (!ret)
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nv_bo_alloc(&bo_nvidia, &nvidia, w, h, 0x10, -1, NOUVEAU_BO_VRAM);
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ret = nv_bo_alloc(&bo_nvidia, &nvidia, w, h, 0x10, -1, NOUVEAU_BO_VRAM);
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nv_bo_alloc(&bo_linear, &linear, w, h, 0, -1, NOUVEAU_BO_GART);
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if (!ret)
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ret = nv_bo_alloc(&bo_linear, &linear, w, h, 0, -1, NOUVEAU_BO_GART);
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if (ret)
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goto out;
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for (y = 0; y < linear.h; ++y) {
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for (y = 0; y < linear.h; ++y) {
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uint8_t *map = bo_linear->map;
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uint8_t *map = bo_linear->map;
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@ -905,13 +879,9 @@ static int test1_swizzle(void)
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goto out;
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goto out;
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}
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}
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ret = nv_bo_alloc(&bo_intel, &intel, w, h, tile_intel_y, prime_fd, 0);
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nv_bo_alloc(&bo_intel, &intel, w, h, tile_intel_y, prime_fd, 0);
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if (!ret)
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nv_bo_alloc(&bo_nvidia, &nvidia, w, h, 0x10, -1, NOUVEAU_BO_VRAM);
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ret = nv_bo_alloc(&bo_nvidia, &nvidia, w, h, 0x10, -1, NOUVEAU_BO_VRAM);
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nv_bo_alloc(&bo_linear, &linear, w, h, 0, -1, NOUVEAU_BO_GART);
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if (!ret)
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ret = nv_bo_alloc(&bo_linear, &linear, w, h, 0, -1, NOUVEAU_BO_GART);
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if (ret)
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goto out;
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noop_intel(test_intel_bo);
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noop_intel(test_intel_bo);
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ptr = bo_linear->map;
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ptr = bo_linear->map;
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@ -968,11 +938,8 @@ static int test2(void)
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uint8_t *ptr;
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uint8_t *ptr;
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uint32_t w = 1024, h = 16, x, y;
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uint32_t w = 1024, h = 16, x, y;
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ret = nv_bo_alloc(&nvbi, &src, w, h, 0, -1, NOUVEAU_BO_GART);
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nv_bo_alloc(&nvbi, &src, w, h, 0, -1, NOUVEAU_BO_GART);
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if (ret >= 0)
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nv_bo_alloc(&nvbo, &dst, w, h, tile_intel_x, -1, NOUVEAU_BO_GART);
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ret = nv_bo_alloc(&nvbo, &dst, w, h, tile_intel_x, -1, NOUVEAU_BO_GART);
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if (ret < 0)
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goto out;
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/* Set up something for our tile that should map into the first
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/* Set up something for our tile that should map into the first
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* y-major tile, assuming my understanding of documentation is
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* y-major tile, assuming my understanding of documentation is
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@ -1008,7 +975,6 @@ static int test2(void)
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if (!ret)
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if (!ret)
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ret = check1_macro(nvbo->map, w/512, h/8);
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ret = check1_macro(nvbo->map, w/512, h/8);
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out:
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nouveau_bo_ref(NULL, &nvbo);
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nouveau_bo_ref(NULL, &nvbo);
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nouveau_bo_ref(NULL, &nvbi);
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nouveau_bo_ref(NULL, &nvbi);
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return ret;
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return ret;
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@ -1070,13 +1036,9 @@ static int test3_base(int tile_src, int tile_dst)
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return -1;
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return -1;
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}
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}
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ret = nv_bo_alloc(&bo_intel, &intel, 2048 * cpp, 768, tile_dst, prime_fd, 0);
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nv_bo_alloc(&bo_intel, &intel, 2048 * cpp, 768, tile_dst, prime_fd, 0);
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if (!ret)
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nv_bo_alloc(&bo_nvidia, &nvidia, 300 * cpp, 300, tile_src, -1, NOUVEAU_BO_VRAM);
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ret = nv_bo_alloc(&bo_nvidia, &nvidia, 300 * cpp, 300, tile_src, -1, NOUVEAU_BO_VRAM);
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nv_bo_alloc(&bo_linear, &linear, 2048 * cpp, 768, 0, -1, NOUVEAU_BO_GART);
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if (!ret)
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ret = nv_bo_alloc(&bo_linear, &linear, 2048 * cpp, 768, 0, -1, NOUVEAU_BO_GART);
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if (ret)
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goto out;
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noop_intel(test_intel_bo);
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noop_intel(test_intel_bo);
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memset(bo_linear->map, 0x80, bo_linear->size);
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memset(bo_linear->map, 0x80, bo_linear->size);
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