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Fix field length of JIP for one-offset-branch in Gen6
Such JIP has 25 bits length in Gen6.
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parent
6983eebf47
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741008e050
@ -1311,7 +1311,10 @@ struct brw_instruction
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{
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{
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GLint JIP:16; /* bspec: both the JIP and UIP are signed 16-bit numbers */
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GLint JIP:16; /* bspec: both the JIP and UIP are signed 16-bit numbers */
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GLint UIP:16;
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GLint UIP:16;
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} branch; /* for branch instructions: brc, brd, if, else, endif, while, break, cont, call, ret, halt, ... */
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} branch_2_offset; /* for Gen6, Gen7 2-offsets branch instructions */
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GLint JIP; /* for Gen6, Gen7 1-offset branch instructions
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Gen6 uses low 25 bits. Gen7 uses low 16 bits. */
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struct {
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struct {
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GLuint function:4;
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GLuint function:4;
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@ -351,12 +351,12 @@ int main(int argc, char **argv)
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entry1->inst_offset - entry->inst_offset;
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entry1->inst_offset - entry->inst_offset;
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int delta = (entry->instruction.header.opcode == BRW_OPCODE_JMPI ? 1 : 0);
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int delta = (entry->instruction.header.opcode == BRW_OPCODE_JMPI ? 1 : 0);
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if (gen_level >= 5)
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if (gen_level >= 5)
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entry->instruction.bits3.branch.JIP = 2 * (offset - delta); // bspec: the jump distance in number of eight-byte units
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entry->instruction.bits3.JIP = 2 * (offset - delta); // bspec: the jump distance in number of eight-byte units
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else
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else
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entry->instruction.bits3.branch.JIP = offset - delta;
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entry->instruction.bits3.JIP = offset - delta;
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if (entry->instruction.header.opcode == BRW_OPCODE_ELSE)
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if (entry->instruction.header.opcode == BRW_OPCODE_ELSE)
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entry->instruction.bits3.branch.UIP = 1;
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entry->instruction.bits3.branch_2_offset.UIP = 1;
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found = 1;
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found = 1;
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break;
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break;
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}
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}
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