mirror of
https://github.com/tiagovignatti/intel-gpu-tools.git
synced 2025-06-25 08:46:27 +00:00
assembler: Port the warning and error reporting to warn()/error()
This way we ensure to have a single place where these are handled. The immediate benefit is that now line numbers are always printed out, which is quite handy. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
This commit is contained in:
Damien Lespiau
parent
e7cca1a3ca
commit
6d3d369535
272
assembler/gram.y
272
assembler/gram.y
@ -133,10 +133,13 @@ static void message(enum message_level level, YYLTYPE *location,
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#define warn(flag, l, fmt, ...) \
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do { \
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if (warning_flags & WARN_ ## flag) \
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message(WARN, location, fmt, ## __VA_ARGS__); \
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message(WARN, l, fmt, ## __VA_ARGS__); \
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} while(0)
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#define error(l, fmt, ...) message(ERROR, location, fmt, ## __VA_ARGS__)
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#define error(l, fmt, ...) \
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do { \
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message(ERROR, l, fmt, ## __VA_ARGS__); \
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} while(0)
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/* like strcmp, but handles NULL pointers */
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static bool strcmp0(const char *s1, const char* s2)
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@ -510,6 +513,18 @@ static void resolve_subnr(struct brw_reg *reg)
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%type <src_operand> indirectsrcoperand
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%type <src_operand> src srcimm imm32reg payload srcacc srcaccimm swizzle
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%type <src_operand> relativelocation relativelocation2
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%code {
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#undef error
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#define error(l, fmt, ...) \
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do { \
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message(ERROR, l, fmt, ## __VA_ARGS__); \
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YYERROR; \
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} while(0)
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}
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%%
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simple_int: INTEGER { $$ = $1; }
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| MINUS INTEGER { $$ = -$2;}
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@ -584,11 +599,9 @@ declare_pragma: DECLARE_PRAGMA STRING declare_base declare_elementsize declare_s
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found = find_register($2);
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if (found) {
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if (!declared_register_equal(®, found)) {
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fprintf(stderr, "Error: %s already defined and "
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"definitions don't agree\n", $2);
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YYERROR;
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}
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if (!declared_register_equal(®, found))
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error(&@1, "%s already defined and definitions "
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"don't agree\n", $2);
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free($2); // $2 has been malloc'ed by strdup
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} else {
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new_reg = malloc(sizeof(struct declared_register));
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@ -694,10 +707,8 @@ relocatableinstruction: ifelseinstruction
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ifelseinstruction: ENDIF
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{
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// for Gen4
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if(IS_GENp(6)) { // For gen6+.
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fprintf(stderr, "ENDIF Syntax error: should be 'ENDIF execsize relativelocation'\n");
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YYERROR;
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}
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if(IS_GENp(6)) // For gen6+.
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error(&@1, "should be 'ENDIF execsize relativelocation'\n");
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memset(&$$, 0, sizeof($$));
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$$.gen.header.opcode = $1;
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$$.gen.header.thread_control |= BRW_THREAD_SWITCH;
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@ -709,10 +720,8 @@ ifelseinstruction: ENDIF
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{
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// for Gen6+
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/* Gen6, Gen7 bspec: predication is prohibited */
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if(!IS_GENp(6)) { // for gen6-
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fprintf(stderr, "ENDIF Syntax error: should be 'ENDIF'\n");
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YYERROR;
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}
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if(!IS_GENp(6)) // for gen6-
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error(&@1, "ENDIF Syntax error: should be 'ENDIF'\n");
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memset(&$$, 0, sizeof($$));
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$$.gen.header.opcode = $1;
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$$.gen.header.execution_size = $2;
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@ -742,24 +751,19 @@ ifelseinstruction: ENDIF
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$$.first_reloc_target = $3.reloc_target;
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$$.first_reloc_offset = $3.imm32;
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} else {
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fprintf(stderr, "'ELSE' instruction is not implemented.\n");
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YYERROR;
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error(&@1, "'ELSE' instruction is not implemented.\n");
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}
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}
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| predicate IF execsize relativelocation
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{
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/* for Gen4, Gen5 */
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/* The branch instructions require that the IP register
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* be the destination and first source operand, while the
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* offset is the second source operand. The offset is added
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* to the pre-incremented IP.
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*/
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/* for Gen6 */
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if(IS_GENp(7)) {
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/* Error in Gen7+. */
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fprintf(stderr, "Syntax error: IF should be 'IF execsize JIP UIP'\n");
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YYERROR;
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}
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if(IS_GENp(7)) /* Error in Gen7+. */
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error(&@2, "IF should be 'IF execsize JIP UIP'\n");
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memset(&$$, 0, sizeof($$));
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set_instruction_predicate(&$$.gen, &$1);
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$$.gen.header.opcode = $2;
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@ -776,10 +780,9 @@ ifelseinstruction: ENDIF
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| predicate IF execsize relativelocation relativelocation
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{
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/* for Gen7+ */
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if(!IS_GENp(7)) {
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fprintf(stderr, "Syntax error: IF should be 'IF execsize relativelocation'\n");
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YYERROR;
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}
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if(!IS_GENp(7))
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error(&@2, "IF should be 'IF execsize relativelocation'\n");
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memset(&$$, 0, sizeof($$));
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set_instruction_predicate(&$$.gen, &$1);
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$$.gen.header.opcode = $2;
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@ -820,8 +823,7 @@ loopinstruction: predicate WHILE execsize relativelocation instoptions
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$$.first_reloc_target = $4.reloc_target;
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$$.first_reloc_offset = $4.imm32;
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} else {
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fprintf(stderr, "'WHILE' instruction is not implemented!\n");
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YYERROR;
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error(&@2, "'WHILE' instruction is not implemented!\n");
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}
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}
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| DO
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@ -955,7 +957,9 @@ unaryinstruction:
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if ($$.header.predicate_control != BRW_PREDICATE_NONE &&
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($1.bits2.da1.flag_reg_nr != $3.flag_reg_nr ||
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$1.bits2.da1.flag_subreg_nr != $3.flag_subreg_nr))
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fprintf(stderr, "WARNING: must use the same flag register if both prediction and conditional modifier are enabled\n");
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warn(ALWAYS, &@3, "must use the same flag register if "
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"both prediction and conditional modifier are "
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"enabled\n");
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$$.bits2.da1.flag_reg_nr = $3.flag_reg_nr;
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$$.bits2.da1.flag_subreg_nr = $3.flag_subreg_nr;
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@ -994,7 +998,9 @@ binaryinstruction:
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if ($$.header.predicate_control != BRW_PREDICATE_NONE &&
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($1.bits2.da1.flag_reg_nr != $3.flag_reg_nr ||
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$1.bits2.da1.flag_subreg_nr != $3.flag_subreg_nr))
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fprintf(stderr, "WARNING: must use the same flag register if both prediction and conditional modifier are enabled\n");
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warn(ALWAYS, &@3, "must use the same flag register if "
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"both prediction and conditional modifier are "
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"enabled\n");
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$$.bits2.da1.flag_reg_nr = $3.flag_reg_nr;
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$$.bits2.da1.flag_subreg_nr = $3.flag_subreg_nr;
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@ -1033,7 +1039,9 @@ binaryaccinstruction:
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if ($$.header.predicate_control != BRW_PREDICATE_NONE &&
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($1.bits2.da1.flag_reg_nr != $3.flag_reg_nr ||
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$1.bits2.da1.flag_subreg_nr != $3.flag_subreg_nr))
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fprintf(stderr, "WARNING: must use the same flag register if both prediction and conditional modifier are enabled\n");
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warn(ALWAYS, &@3, "must use the same flag register if "
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"both prediction and conditional modifier are "
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"enabled\n");
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$$.bits2.da1.flag_reg_nr = $3.flag_reg_nr;
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$$.bits2.da1.flag_subreg_nr = $3.flag_subreg_nr;
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@ -1082,7 +1090,9 @@ trinaryinstruction:
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if ($$.header.predicate_control != BRW_PREDICATE_NONE &&
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($1.bits2.da1.flag_reg_nr != $3.flag_reg_nr ||
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$1.bits2.da1.flag_subreg_nr != $3.flag_subreg_nr))
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fprintf(stderr, "WARNING: must use the same flag register if both prediction and conditional modifier are enabled\n");
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warn(ALWAYS, &@3, "must use the same flag register if "
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"both prediction and conditional modifier are "
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"enabled\n");
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}
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}
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;
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@ -1176,8 +1186,8 @@ sendinstruction: predicate SEND execsize exp post_dst payload msgtarget
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if ($7.reg.type != BRW_REGISTER_TYPE_UD &&
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$7.reg.type != BRW_REGISTER_TYPE_D &&
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$7.reg.type != BRW_REGISTER_TYPE_V) {
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fprintf (stderr, "%d: non-int D/UD/V representation: %d,type=%d\n", yylineno, $7.reg.dw1.ud, $7.reg.type);
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YYERROR;
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error (&@7, "non-int D/UD/V representation: %d,"
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"type=%d\n", $7.reg.dw1.ud, $7.reg.type);
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}
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memset(&$$, 0, sizeof($$));
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$$.header.opcode = $2;
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@ -1197,16 +1207,14 @@ sendinstruction: predicate SEND execsize exp post_dst payload msgtarget
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{
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struct src_operand src0;
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if (!IS_GENp(6)) {
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fprintf(stderr, "error: the syntax of send instruction\n");
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YYERROR;
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}
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if (!IS_GENp(6))
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error(&@2, "the syntax of send instruction\n");
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if ($7.reg.type != BRW_REGISTER_TYPE_UD &&
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$7.reg.type != BRW_REGISTER_TYPE_D &&
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$7.reg.type != BRW_REGISTER_TYPE_V) {
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fprintf (stderr, "%d: non-int D/UD/V representation: %d,type=%d\n", yylineno, $7.reg.dw1.ud, $7.reg.type);
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YYERROR;
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error(&@7,"non-int D/UD/V representation: %d,"
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"type=%d\n", $7.reg.dw1.ud, $7.reg.type);
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}
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memset(&$$, 0, sizeof($$));
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@ -1242,17 +1250,14 @@ sendinstruction: predicate SEND execsize exp post_dst payload msgtarget
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{
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struct src_operand src0;
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if (!IS_GENp(6)) {
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fprintf(stderr, "error: the syntax of send instruction\n");
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YYERROR;
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}
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if (!IS_GENp(6))
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error(&@2, "the syntax of send instruction\n");
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if ($7.reg.file != BRW_ARCHITECTURE_REGISTER_FILE ||
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($7.reg.nr & 0xF0) != BRW_ARF_ADDRESS ||
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($7.reg.nr & 0x0F) != 0 ||
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$7.reg.subnr != 0) {
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fprintf (stderr, "%d: scalar register must be a0.0<0;1,0>:ud\n", yylineno);
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YYERROR;
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error (&@7, "scalar register must be a0.0<0;1,0>:ud\n");
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}
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memset(&$$, 0, sizeof($$));
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@ -1287,8 +1292,8 @@ sendinstruction: predicate SEND execsize exp post_dst payload msgtarget
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if ($8.reg.type != BRW_REGISTER_TYPE_UD &&
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$8.reg.type != BRW_REGISTER_TYPE_D &&
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$8.reg.type != BRW_REGISTER_TYPE_V) {
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fprintf (stderr, "%d: non-int D/UD/V representation: %d,type=%d\n", yylineno, $8.reg.dw1.ud, $8.reg.type);
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YYERROR;
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error(&@8, "non-int D/UD/V representation: %d,"
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"type=%d\n", $8.reg.dw1.ud, $8.reg.type);
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}
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memset(&$$, 0, sizeof($$));
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$$.header.opcode = $2;
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@ -1476,8 +1481,7 @@ msgtarget: NULL_TOKEN
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| MATH math_function saturate math_signed math_scalar
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{
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if (IS_GENp(6)) {
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fprintf (stderr, "Gen6+ doesn't have math function\n");
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YYERROR;
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error (&@1, "Gen6+ doesn't have math function\n");
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} else if (IS_GENx(5)) {
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$$.bits2.send_gen5.sfid = BRW_SFID_MATH;
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$$.bits3.generic_gen5.header_present = 0;
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@ -1682,16 +1686,14 @@ msgtarget: NULL_TOKEN
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$$.bits3.vme_gen6.message_type = $9;
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$$.bits3.generic_gen5.header_present = 1;
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} else {
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fprintf (stderr, "Gen6- doesn't have vme function\n");
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YYERROR;
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error (&@1, "Gen6- doesn't have vme function\n");
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}
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}
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| CRE LPAREN INTEGER COMMA INTEGER RPAREN
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{
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if (gen_level < 75) {
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fprintf (stderr, "Below Gen7.5 doesn't have CRE function\n");
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YYERROR;
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}
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if (gen_level < 75)
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error (&@1, "Below Gen7.5 doesn't have CRE function\n");
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$$.bits3.generic.msg_target = HSW_SFID_CRE;
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$$.bits2.send_gen5.sfid = HSW_SFID_CRE;
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@ -1711,8 +1713,7 @@ msgtarget: NULL_TOKEN
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$3 != GEN6_SFID_DATAPORT_RENDER_CACHE &&
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$3 != GEN6_SFID_DATAPORT_CONSTANT_CACHE &&
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$3 != GEN7_SFID_DATAPORT_DATA_CACHE) {
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fprintf (stderr, "error: wrong cache type\n");
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YYERROR;
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error (&@3, "error: wrong cache type\n");
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}
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$$.bits3.gen7_dp.category = $11;
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@ -1723,8 +1724,7 @@ msgtarget: NULL_TOKEN
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if ($3 != GEN6_SFID_DATAPORT_SAMPLER_CACHE &&
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$3 != GEN6_SFID_DATAPORT_RENDER_CACHE &&
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$3 != GEN6_SFID_DATAPORT_CONSTANT_CACHE) {
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fprintf (stderr, "error: wrong cache type\n");
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YYERROR;
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error (&@3, "error: wrong cache type\n");
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}
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$$.bits3.gen6_dp.send_commit_msg = $11;
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@ -1732,8 +1732,7 @@ msgtarget: NULL_TOKEN
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$$.bits3.gen6_dp.msg_control = $7;
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$$.bits3.gen6_dp.msg_type = $5;
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} else if (!IS_GENp(5)) {
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fprintf (stderr, "Gen6- doesn't support data port for sampler/render/constant/data cache\n");
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YYERROR;
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error (&@1, "Gen6- doesn't support data port for sampler/render/constant/data cache\n");
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}
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}
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;
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@ -1838,10 +1837,8 @@ symbol_reg: STRING %prec STR_SYMBOL_REG
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{
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struct declared_register *dcl_reg = find_register($1);
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if (dcl_reg == NULL) {
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fprintf(stderr, "can't find register %s\n", $1);
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YYERROR;
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}
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if (dcl_reg == NULL)
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error(&@1, "can't find register %s\n", $1);
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memcpy(&$$, dcl_reg, sizeof(*dcl_reg));
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free($1); // $1 has been malloc'ed by strdup
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@ -1856,10 +1853,8 @@ symbol_reg_p: STRING LPAREN exp RPAREN
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{
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struct declared_register *dcl_reg = find_register($1);
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if (dcl_reg == NULL) {
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fprintf(stderr, "can't find register %s\n", $1);
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YYERROR;
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}
|
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if (dcl_reg == NULL)
|
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error(&@1, "can't find register %s\n", $1);
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memcpy(&$$, dcl_reg, sizeof(*dcl_reg));
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$$.reg.nr += $3;
|
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@ -1869,10 +1864,8 @@ symbol_reg_p: STRING LPAREN exp RPAREN
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{
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struct declared_register *dcl_reg = find_register($1);
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if (dcl_reg == NULL) {
|
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fprintf(stderr, "can't find register %s\n", $1);
|
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YYERROR;
|
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}
|
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if (dcl_reg == NULL)
|
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error(&@1, "can't find register %s\n", $1);
|
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memcpy(&$$, dcl_reg, sizeof(*dcl_reg));
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$$.reg.nr += $3;
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@ -1940,8 +1933,7 @@ imm32reg: imm32 srcimmtype
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d = $1.u.d;
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break;
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default:
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fprintf (stderr, "%d: non-int D/UD/V/VF representation: %d,type=%d\n", yylineno, $1.r, $2);
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YYERROR;
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error (&@2, "non-int D/UD/V/VF representation: %d,type=%d\n", $1.r, $2);
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}
|
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break;
|
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case BRW_REGISTER_TYPE_UW:
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@ -1951,8 +1943,7 @@ imm32reg: imm32 srcimmtype
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d = $1.u.d;
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break;
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default:
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fprintf (stderr, "non-int W/UW representation\n");
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YYERROR;
|
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error (&@2, "non-int W/UW representation\n");
|
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}
|
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d &= 0xffff;
|
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d |= d << 16;
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@ -1966,8 +1957,7 @@ imm32reg: imm32 srcimmtype
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intfloat.f = (float) $1.u.d;
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break;
|
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default:
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fprintf (stderr, "non-float F representation\n");
|
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YYERROR;
|
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error (&@2, "non-float F representation\n");
|
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}
|
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d = intfloat.i;
|
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break;
|
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@ -1977,8 +1967,7 @@ imm32reg: imm32 srcimmtype
|
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YYERROR;
|
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#endif
|
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default:
|
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fprintf(stderr, "unknown immediate type %d\n", $2);
|
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YYERROR;
|
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error(&@2, "unknown immediate type %d\n", $2);
|
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}
|
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memset (&$$, '\0', sizeof ($$));
|
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$$.reg.file = BRW_IMMEDIATE_VALUE;
|
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@ -2145,11 +2134,8 @@ indirectsrcoperand:
|
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*/
|
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addrparam: addrreg COMMA immaddroffset
|
||||
{
|
||||
if ($3 < -512 || $3 > 511) {
|
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fprintf(stderr, "Address immediate offset %d out of"
|
||||
"range %d\n", $3, yylineno);
|
||||
YYERROR;
|
||||
}
|
||||
if ($3 < -512 || $3 > 511)
|
||||
error(&@3, "Address immediate offset %d out of range\n", $3);
|
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memset (&$$, '\0', sizeof ($$));
|
||||
$$.subnr = $1.subnr;
|
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$$.dw1.bits.indirect_offset = $3;
|
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@ -2220,11 +2206,9 @@ indirectmsgreg: MSGREGFILE LSQUARE addrparam RSQUARE
|
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|
||||
addrreg: ADDRESSREG subregnum
|
||||
{
|
||||
if ($1 != 0) {
|
||||
fprintf(stderr,
|
||||
"address register number %d out of range", $1);
|
||||
YYERROR;
|
||||
}
|
||||
if ($1 != 0)
|
||||
error(&@2, "address register number %d out of range", $1);
|
||||
|
||||
memset (&$$, '\0', sizeof ($$));
|
||||
$$.file = BRW_ARCHITECTURE_REGISTER_FILE;
|
||||
$$.nr = BRW_ARF_ADDRESS | $1;
|
||||
@ -2234,11 +2218,8 @@ addrreg: ADDRESSREG subregnum
|
||||
|
||||
accreg: ACCREG subregnum
|
||||
{
|
||||
if ($1 > 1) {
|
||||
fprintf(stderr,
|
||||
"accumulator register number %d out of range", $1);
|
||||
YYERROR;
|
||||
}
|
||||
if ($1 > 1)
|
||||
error(&@1, "accumulator register number %d out of range", $1);
|
||||
memset (&$$, '\0', sizeof ($$));
|
||||
$$.file = BRW_ARCHITECTURE_REGISTER_FILE;
|
||||
$$.nr = BRW_ARF_ACCUMULATOR | $1;
|
||||
@ -2250,16 +2231,11 @@ flagreg: FLAGREG subregnum
|
||||
{
|
||||
if ((!IS_GENp(7) && $1) > 0 ||
|
||||
(IS_GENp(7) && $1 > 1)) {
|
||||
fprintf(stderr,
|
||||
"flag register number %d out of range\n", $1);
|
||||
YYERROR;
|
||||
error(&@2, "flag register number %d out of range\n", $1);
|
||||
}
|
||||
|
||||
if ($2 > 1) {
|
||||
fprintf(stderr,
|
||||
"flag subregister number %d out of range\n", $1);
|
||||
YYERROR;
|
||||
}
|
||||
if ($2 > 1)
|
||||
error(&@2, "flag subregister number %d out of range\n", $1);
|
||||
|
||||
memset (&$$, '\0', sizeof ($$));
|
||||
$$.file = BRW_ARCHITECTURE_REGISTER_FILE;
|
||||
@ -2270,11 +2246,9 @@ flagreg: FLAGREG subregnum
|
||||
|
||||
maskreg: MASKREG subregnum
|
||||
{
|
||||
if ($1 > 0) {
|
||||
fprintf(stderr,
|
||||
"mask register number %d out of range", $1);
|
||||
YYERROR;
|
||||
}
|
||||
if ($1 > 0)
|
||||
error(&@1, "mask register number %d out of range", $1);
|
||||
|
||||
memset (&$$, '\0', sizeof ($$));
|
||||
$$.file = BRW_ARCHITECTURE_REGISTER_FILE;
|
||||
$$.nr = BRW_ARF_MASK;
|
||||
@ -2294,11 +2268,8 @@ mask_subreg: AMASK | IMASK | LMASK | CMASK
|
||||
|
||||
maskstackreg: MASKSTACKREG subregnum
|
||||
{
|
||||
if ($1 > 0) {
|
||||
fprintf(stderr,
|
||||
"mask stack register number %d out of range", $1);
|
||||
YYERROR;
|
||||
}
|
||||
if ($1 > 0)
|
||||
error(&@1, "mask stack register number %d out of range", $1);
|
||||
memset (&$$, '\0', sizeof ($$));
|
||||
$$.file = BRW_ARCHITECTURE_REGISTER_FILE;
|
||||
$$.nr = BRW_ARF_MASK_STACK;
|
||||
@ -2319,11 +2290,8 @@ maskstack_subreg: IMS | LMS
|
||||
/*
|
||||
maskstackdepthreg: MASKSTACKDEPTHREG subregnum
|
||||
{
|
||||
if ($1 > 0) {
|
||||
fprintf(stderr,
|
||||
"mask stack register number %d out of range", $1);
|
||||
YYERROR;
|
||||
}
|
||||
if ($1 > 0)
|
||||
error(&@1, "mask stack register number %d out of range", $1);
|
||||
memset (&$$, '\0', sizeof ($$));
|
||||
$$.reg_file = BRW_ARCHITECTURE_REGISTER_FILE;
|
||||
$$.reg_nr = BRW_ARF_MASK_STACK_DEPTH;
|
||||
@ -2346,12 +2314,10 @@ notifyreg: NOTIFYREG regtype
|
||||
{
|
||||
int num_notifyreg = (IS_GENp(6)) ? 3 : 2;
|
||||
|
||||
if ($1 > num_notifyreg) {
|
||||
fprintf(stderr,
|
||||
"notification register number %d out of range",
|
||||
if ($1 > num_notifyreg)
|
||||
error(&@1, "notification register number %d out of range",
|
||||
$1);
|
||||
YYERROR;
|
||||
}
|
||||
|
||||
memset (&$$, '\0', sizeof ($$));
|
||||
$$.file = BRW_ARCHITECTURE_REGISTER_FILE;
|
||||
|
||||
@ -2382,16 +2348,12 @@ notifyreg: NOTIFYREG regtype
|
||||
|
||||
statereg: STATEREG subregnum
|
||||
{
|
||||
if ($1 > 0) {
|
||||
fprintf(stderr,
|
||||
"state register number %d out of range", $1);
|
||||
YYERROR;
|
||||
}
|
||||
if ($2 > 1) {
|
||||
fprintf(stderr,
|
||||
"state subregister number %d out of range", $1);
|
||||
YYERROR;
|
||||
}
|
||||
if ($1 > 0)
|
||||
error(&@1, "state register number %d out of range", $1);
|
||||
|
||||
if ($2 > 1)
|
||||
error(&@2, "state subregister number %d out of range", $1);
|
||||
|
||||
memset (&$$, '\0', sizeof ($$));
|
||||
$$.file = BRW_ARCHITECTURE_REGISTER_FILE;
|
||||
$$.nr = BRW_ARF_STATE | $1;
|
||||
@ -2401,16 +2363,11 @@ statereg: STATEREG subregnum
|
||||
|
||||
controlreg: CONTROLREG subregnum
|
||||
{
|
||||
if ($1 > 0) {
|
||||
fprintf(stderr,
|
||||
"control register number %d out of range", $1);
|
||||
YYERROR;
|
||||
}
|
||||
if ($2 > 2) {
|
||||
fprintf(stderr,
|
||||
"control subregister number %d out of range", $1);
|
||||
YYERROR;
|
||||
}
|
||||
if ($1 > 0)
|
||||
error(&@1, "control register number %d out of range", $1);
|
||||
|
||||
if ($2 > 2)
|
||||
error(&@2, "control subregister number %d out of range", $1);
|
||||
memset (&$$, '\0', sizeof ($$));
|
||||
$$.file = BRW_ARCHITECTURE_REGISTER_FILE;
|
||||
$$.nr = BRW_ARF_CONTROL | $1;
|
||||
@ -2440,12 +2397,8 @@ nullreg: NULL_TOKEN
|
||||
relativelocation:
|
||||
simple_int
|
||||
{
|
||||
if (($1 > 32767) || ($1 < -32768)) {
|
||||
fprintf(stderr,
|
||||
"error: relative offset %d out of range \n",
|
||||
$1);
|
||||
YYERROR;
|
||||
}
|
||||
if (($1 > 32767) || ($1 < -32768))
|
||||
error(&@1, "error: relative offset %d out of range \n", $1);
|
||||
|
||||
memset (&$$, '\0', sizeof ($$));
|
||||
$$.reg.file = BRW_IMMEDIATE_VALUE;
|
||||
@ -2520,9 +2473,9 @@ dstregion: /* empty */
|
||||
/* Returns a value for a horiz_stride field of an
|
||||
* instruction.
|
||||
*/
|
||||
if ($2 != 1 && $2 != 2 && $2 != 4) {
|
||||
fprintf(stderr, "Invalid horiz size %d\n", $2);
|
||||
}
|
||||
if ($2 != 1 && $2 != 2 && $2 != 4)
|
||||
error(&@2, "Invalid horiz size %d\n", $2);
|
||||
|
||||
$$ = ffs($2);
|
||||
}
|
||||
;
|
||||
@ -2723,10 +2676,9 @@ execsize: /* empty */ %prec EMPTEXECSIZE
|
||||
* instruction.
|
||||
*/
|
||||
if ($2 != 1 && $2 != 2 && $2 != 4 && $2 != 8 && $2 != 16 &&
|
||||
$2 != 32) {
|
||||
fprintf(stderr, "Invalid execution size %d\n", $2);
|
||||
YYERROR;
|
||||
}
|
||||
$2 != 32)
|
||||
error(&@2, "Invalid execution size %d\n", $2);
|
||||
|
||||
$$ = ffs($2) - 1;
|
||||
}
|
||||
;
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user