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https://github.com/tiagovignatti/intel-gpu-tools.git
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igt/gem_workarounds: Convert to real GPU hang injection
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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6f7372f664
commit
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@ -27,25 +27,11 @@
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#define _GNU_SOURCE
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#include "igt.h"
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#include <stdbool.h>
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#include <unistd.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <fcntl.h>
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#include <inttypes.h>
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#include <errno.h>
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#include <sys/stat.h>
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#include <sys/ioctl.h>
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#include <sys/mman.h>
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#include <time.h>
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#include <signal.h>
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enum operation {
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GPU_RESET = 0x01,
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SUSPEND_RESUME = 0x02,
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SIMPLE_READ = 0x03,
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GPU_RESET,
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SUSPEND_RESUME,
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SIMPLE_READ,
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};
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struct intel_wa_reg {
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@ -54,57 +40,21 @@ struct intel_wa_reg {
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uint32_t mask;
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};
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static int drm_fd;
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static uint32_t devid;
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static drm_intel_bufmgr *bufmgr;
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struct intel_batchbuffer *batch;
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static int num_wa_regs;
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static struct intel_wa_reg *wa_regs;
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static int num_wa_regs;
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static void wait_gpu(void)
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{
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struct drm_i915_gem_execbuffer2 execbuf;
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struct drm_i915_gem_exec_object2 gem_exec;
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uint32_t b[2] = {MI_BATCH_BUFFER_END};
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memset(&gem_exec, 0, sizeof(gem_exec));
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gem_exec.handle = gem_create(drm_fd, 4096);
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gem_write(drm_fd, gem_exec.handle, 0, b, sizeof(b));
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memset(&execbuf, 0, sizeof(execbuf));
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execbuf.buffers_ptr = (uintptr_t)&gem_exec;
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execbuf.buffer_count = 1;
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execbuf.batch_len = sizeof(b);
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drmIoctl(drm_fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf);
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gem_sync(drm_fd, gem_exec.handle);
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gem_close(drm_fd, gem_exec.handle);
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int fd = drm_open_driver(DRIVER_INTEL);
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gem_quiescent_gpu(fd);
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close(fd);
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}
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static void test_hang_gpu(void)
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{
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int retry_count = 30;
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enum stop_ring_flags flags;
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igt_assert(retry_count);
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igt_set_stop_rings(STOP_RING_DEFAULTS);
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wait_gpu();
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while(retry_count--) {
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flags = igt_get_stop_rings();
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if (flags == 0)
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break;
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igt_info("gpu hang not yet cleared, retries left %d\n", retry_count);
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sleep(1);
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}
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flags = igt_get_stop_rings();
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if (flags)
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igt_set_stop_rings(STOP_RING_NONE);
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int fd = drm_open_driver(DRIVER_INTEL);
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igt_post_hang_ring(fd, igt_hang_ring(fd, I915_EXEC_DEFAULT));
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close(fd);
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}
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static void test_suspend_resume(void)
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@ -117,8 +67,6 @@ static int workaround_fail_count(void)
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{
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int i, fail_count = 0;
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intel_register_access_init(intel_get_pci_device(), 0);
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/* There is a small delay after coming ot of rc6 to the correct
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render context values will get loaded by hardware (bdw,chv).
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This here ensures that we have the correct context loaded before
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@ -145,8 +93,6 @@ static int workaround_fail_count(void)
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}
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}
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intel_register_access_fini();
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return fail_count;
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}
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@ -176,48 +122,44 @@ static void check_workarounds(enum operation op)
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igt_main
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{
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igt_fixture {
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int i;
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int fd;
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int ret;
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struct pci_device *pci_dev;
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FILE *file;
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char *line = NULL;
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size_t line_size;
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int i;
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drm_fd = drm_open_driver(DRIVER_INTEL);
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pci_dev = intel_get_pci_device();
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igt_require(pci_dev);
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bufmgr = drm_intel_bufmgr_gem_init(drm_fd, 4096);
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devid = intel_get_drm_devid(drm_fd);
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batch = intel_batchbuffer_alloc(bufmgr, devid);
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intel_register_access_init(pci_dev, 0);
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fd = igt_debugfs_open("i915_wa_registers", O_RDONLY);
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igt_assert(fd >= 0);
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file = fdopen(fd, "r");
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igt_assert(file > 0);
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ret = getline(&line, &line_size, file);
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igt_assert(ret > 0);
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file = igt_debugfs_fopen("i915_wa_registers", "r");
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igt_assert(getline(&line, &line_size, file) > 0);
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igt_debug("i915_wa_registers: %s", line);
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sscanf(line, "Workarounds applied: %d", &num_wa_regs);
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if (IS_BROADWELL(devid) ||
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IS_CHERRYVIEW(devid))
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if (IS_BROADWELL(pci_dev->device_id) ||
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IS_CHERRYVIEW(pci_dev->device_id))
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igt_assert(num_wa_regs > 0);
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else
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igt_assert(num_wa_regs >= 0);
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wa_regs = malloc(num_wa_regs * sizeof(*wa_regs));
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igt_assert(wa_regs);
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i = 0;
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while (getline(&line, &line_size, file) > 0) {
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sscanf(line, "0x%X: 0x%08X, mask: 0x%08X",
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&wa_regs[i].addr, &wa_regs[i].value,
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&wa_regs[i].mask);
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++i;
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igt_debug("%s", line);
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igt_assert(i < num_wa_regs);
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if (sscanf(line, "0x%X: 0x%08X, mask: 0x%08X",
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&wa_regs[i].addr,
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&wa_regs[i].value,
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&wa_regs[i].mask) == 3)
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i++;
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}
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free(line);
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fclose(file);
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close(fd);
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}
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igt_subtest("read")
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@ -231,6 +173,7 @@ igt_main
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igt_fixture {
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free(wa_regs);
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close(drm_fd);
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intel_register_access_fini();
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}
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}
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