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gem_pipe_control_store_loop: BDW update

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I've opted to not use the PIPE_CONTROL w/a for now. I am unclear if it
is actually required (the test does pass).

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
This commit is contained in:
Ben Widawsky 2013-12-05 14:14:35 -08:00
parent 40b586188c
commit 672911d714
3 changed files with 31 additions and 4 deletions
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15
lib/intel_batchbuffer.h
View File

@ -112,6 +112,21 @@ intel_batchbuffer_require_space(struct intel_batchbuffer *batch,
} \ } \
} while(0) } while(0)
#define COLOR_BLIT_COPY_BATCH_START(devid, flags) do { \
if (intel_gen(devid) >= 8) { \
BEGIN_BATCH(8); \
OUT_BATCH(MI_NOOP); \
OUT_BATCH(XY_COLOR_BLT_CMD_NOLEN | 0x5 | \
COLOR_BLT_WRITE_ALPHA | \
XY_COLOR_BLT_WRITE_RGB); \
} else { \
BEGIN_BATCH(6); \
OUT_BATCH(XY_COLOR_BLT_CMD_NOLEN | 0x4 | \
COLOR_BLT_WRITE_ALPHA | \
XY_COLOR_BLT_WRITE_RGB); \
} \
} while(0)
#define BLIT_RELOC_UDW(devid) do { \ #define BLIT_RELOC_UDW(devid) do { \
if (intel_gen(devid) >= 8) { \ if (intel_gen(devid) >= 8) { \
OUT_BATCH(0); \ OUT_BATCH(0); \

3
lib/intel_reg.h
View File

@ -2709,7 +2709,8 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define COLOR_BLT_WRITE_ALPHA (1<<21) #define COLOR_BLT_WRITE_ALPHA (1<<21)
#define COLOR_BLT_WRITE_RGB (1<<20) #define COLOR_BLT_WRITE_RGB (1<<20)
#define XY_COLOR_BLT_CMD ((2<<29)|(0x50<<22)|(0x4)) #define XY_COLOR_BLT_CMD_NOLEN ((2<<29)|(0x50<<22))
#define XY_COLOR_BLT_CMD (XY_COLOR_BLT_CMD_NOLEN|(0x4))
#define XY_COLOR_BLT_WRITE_ALPHA (1<<21) #define XY_COLOR_BLT_WRITE_ALPHA (1<<21)
#define XY_COLOR_BLT_WRITE_RGB (1<<20) #define XY_COLOR_BLT_WRITE_RGB (1<<20)
#define XY_COLOR_BLT_TILED (1<<11) #define XY_COLOR_BLT_TILED (1<<11)

17
tests/gem_pipe_control_store_loop.c
View File

@ -76,8 +76,7 @@ store_pipe_control_loop(bool preuse_buffer)
igt_assert(target_bo); igt_assert(target_bo);
if (preuse_buffer) { if (preuse_buffer) {
BEGIN_BATCH(6); COLOR_BLIT_COPY_BATCH_START(devid, 0);
OUT_BATCH(XY_COLOR_BLT_CMD | COLOR_BLT_WRITE_ALPHA | XY_COLOR_BLT_WRITE_RGB);
OUT_BATCH((3 << 24) | (0xf0 << 16) | 64); OUT_BATCH((3 << 24) | (0xf0 << 16) | 64);
OUT_BATCH(0); OUT_BATCH(0);
OUT_BATCH(1 << 16 | 1); OUT_BATCH(1 << 16 | 1);
@ -90,6 +89,7 @@ store_pipe_control_loop(bool preuse_buffer)
OUT_RELOC(target_bo, OUT_RELOC(target_bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
0); 0);
BLIT_RELOC_UDW(devid);
OUT_BATCH(0xdeadbeef); OUT_BATCH(0xdeadbeef);
ADVANCE_BATCH(); ADVANCE_BATCH();
@ -101,7 +101,18 @@ store_pipe_control_loop(bool preuse_buffer)
/* gem_storedw_batches_loop.c is a bit overenthusiastic with /* gem_storedw_batches_loop.c is a bit overenthusiastic with
* creating new batchbuffers - with buffer reuse disabled, the * creating new batchbuffers - with buffer reuse disabled, the
* support code will do that for us. */ * support code will do that for us. */
if (intel_gen(devid) >= 6) { if (intel_gen(devid) >= 8) {
BEGIN_BATCH(5);
OUT_BATCH(GFX_OP_PIPE_CONTROL + 1);
OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);
OUT_RELOC(target_bo,
I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
PIPE_CONTROL_GLOBAL_GTT);
BLIT_RELOC_UDW(devid);
OUT_BATCH(val); /* write data */
ADVANCE_BATCH();
} else if (intel_gen(devid) >= 6) {
/* work-around hw issue, see intel_emit_post_sync_nonzero_flush /* work-around hw issue, see intel_emit_post_sync_nonzero_flush
* in mesa sources. */ * in mesa sources. */
BEGIN_BATCH(4); BEGIN_BATCH(4);