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igt: Add gem_streaming_writes
This tries to replicate the missing barrier observed when using asynchronous mmap(wc) on byt. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson
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1
tests/.gitignore
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1
tests/.gitignore
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@ -100,6 +100,7 @@ gem_storedw_loop_blt
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gem_storedw_loop_bsd
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gem_storedw_loop_render
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gem_storedw_loop_vebox
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gem_streaming_writes
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gem_stress
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gem_threaded_access_tiled
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gem_tiled_blits
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@ -54,6 +54,7 @@ TESTS_progs_M = \
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gem_ringfill \
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gem_set_tiling_vs_blt \
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gem_storedw_batches_loop \
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gem_streaming_writes \
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gem_tiled_blits \
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gem_tiled_partial_pwrite_pread \
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gem_userptr_blits \
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214
tests/gem_streaming_writes.c
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214
tests/gem_streaming_writes.c
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@ -0,0 +1,214 @@
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/*
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* Copyright © 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Chris Wilson <chris@chris-wilson.co.uk>
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*
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*/
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#define _GNU_SOURCE
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#include <unistd.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <fcntl.h>
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#include <inttypes.h>
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#include <pthread.h>
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#include <errno.h>
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#include <sys/stat.h>
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#include <sys/ioctl.h>
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#include "drm.h"
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#include "ioctl_wrappers.h"
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#include "drmtest.h"
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#include "igt_debugfs.h"
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#include "igt_aux.h"
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#include "intel_chipset.h"
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#define OBJECT_SIZE 256*1024
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#define CHUNK_SIZE 32
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#define COPY_BLT_CMD (2<<29|0x53<<22|0x6)
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#define BLT_WRITE_ALPHA (1<<21)
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#define BLT_WRITE_RGB (1<<20)
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#define BLT_WRITE_ARGB (BLT_WRITE_ALPHA | BLT_WRITE_RGB)
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IGT_TEST_DESCRIPTION("Test of streaming writes into active GPU sources");
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static void test_streaming(int fd, int mode)
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{
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const int has_64bit_reloc = intel_gen(intel_get_drm_devid(fd)) >= 8;
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struct drm_i915_gem_execbuffer2 execbuf;
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struct drm_i915_gem_exec_object2 exec[3];
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struct drm_i915_gem_relocation_entry reloc[2];
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uint32_t tmp[] = { MI_BATCH_BUFFER_END };
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uint64_t __src_offset, __dst_offset;
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uint32_t *s, *d;
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uint32_t offset;
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struct {
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uint32_t handle;
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uint64_t offset;
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} *batch;
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int i;
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memset(exec, 0, sizeof(exec));
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exec[0].handle = gem_create(fd, OBJECT_SIZE);
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#define dst exec[0].handle
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#define dst_offset exec[0].offset
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exec[1].handle = gem_create(fd, OBJECT_SIZE);
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#define src exec[1].handle
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#define src_offset exec[1].offset
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switch (mode) {
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case 0: /* cpu/snoop */
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gem_set_caching(fd, src, I915_CACHING_CACHED);
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s = gem_mmap__cpu(fd, src, 0, OBJECT_SIZE, PROT_READ | PROT_WRITE);
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break;
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case 1: /* gtt */
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s = gem_mmap__gtt(fd, src, OBJECT_SIZE, PROT_READ | PROT_WRITE);
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break;
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case 2: /* wc */
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s = gem_mmap__wc(fd, src, 0, OBJECT_SIZE, PROT_READ | PROT_WRITE);
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break;
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}
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igt_assert(s);
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d = gem_mmap__cpu(fd, dst, 0, OBJECT_SIZE, PROT_READ);
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igt_assert(d);
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gem_write(fd, src, 0, tmp, sizeof(tmp));
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memset(&execbuf, 0, sizeof(execbuf));
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execbuf.buffers_ptr = (uintptr_t)exec;
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execbuf.buffer_count = 2;
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gem_execbuf(fd, &execbuf);
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/* We assume that the active objects are fixed to avoid relocations */
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__src_offset = src_offset;
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__dst_offset = dst_offset;
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memset(reloc, 0, sizeof(reloc));
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reloc[0].offset = 4 * sizeof(uint32_t);
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reloc[0].delta = 0;
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reloc[0].target_handle = dst;
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reloc[0].presumed_offset = dst_offset;
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reloc[0].read_domains = I915_GEM_DOMAIN_RENDER;
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reloc[0].write_domain = I915_GEM_DOMAIN_RENDER;
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reloc[1].offset = 7 * sizeof(uint32_t);
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if (has_64bit_reloc)
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reloc[1].offset += sizeof(uint32_t);
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reloc[1].delta = 0;
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reloc[1].target_handle = src;
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reloc[1].presumed_offset = src_offset;
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reloc[1].read_domains = I915_GEM_DOMAIN_RENDER;
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reloc[1].write_domain = 0;
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exec[2].relocation_count = 2;
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exec[2].relocs_ptr = (uintptr_t)reloc;
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execbuf.buffer_count = 3;
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execbuf.flags = I915_EXEC_NO_RELOC;
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if (gem_has_blt(fd))
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execbuf.flags |= I915_EXEC_BLT;
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batch = malloc(sizeof(*batch) * (OBJECT_SIZE / CHUNK_SIZE));
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for (i = 0; i < OBJECT_SIZE / CHUNK_SIZE; i++) {
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unsigned x = (i * CHUNK_SIZE) % 4096 >> 2;
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unsigned y = (i * CHUNK_SIZE) / 4096;
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uint32_t *b;
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int j;
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batch[i].handle = gem_create(fd, 4096);
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batch[i].offset = 0;
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b = gem_mmap__cpu(fd, batch[i].handle, 0, 4096, PROT_WRITE);
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igt_assert(b);
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j = 0;
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b[j] = COPY_BLT_CMD | BLT_WRITE_ARGB;
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if (has_64bit_reloc)
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b[j] += 2;
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j++;
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b[j++] = 0xcc << 16 | 1 << 25 | 1 << 24 | 4096;
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b[j++] = (y << 16) | x;
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b[j++] = ((y+1) << 16) | (x + (CHUNK_SIZE >> 2));
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b[j++] = dst_offset;
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if (has_64bit_reloc)
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b[j++] = dst_offset >> 32;
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b[j++] = (y << 16) | x;
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b[j++] = 4096;
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b[j++] = src_offset;
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if (has_64bit_reloc)
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b[j++] = src_offset >> 32;
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b[j++] = MI_BATCH_BUFFER_END;
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munmap(b, 4096);
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}
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for (int pass = 0; pass < 256; pass++) {
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int domain = mode ? I915_GEM_DOMAIN_GTT : I915_GEM_DOMAIN_CPU;
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gem_set_domain(fd, src, domain, domain);
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/* Now copy from the src to the dst in 32byte chunks */
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for (offset = 0; offset < OBJECT_SIZE; offset += CHUNK_SIZE) {
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for (i = 0; i < CHUNK_SIZE/4; i++)
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s[offset/4 + i] = (OBJECT_SIZE*pass + offset)/4 + i;
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exec[2].handle = batch[offset/CHUNK_SIZE].handle;
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exec[2].offset = batch[offset/CHUNK_SIZE].offset;
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gem_execbuf(fd, &execbuf);
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igt_assert(__src_offset == src_offset);
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igt_assert(__dst_offset == dst_offset);
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batch[offset/CHUNK_SIZE].offset = exec[2].offset;
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}
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gem_set_domain(fd, dst, I915_GEM_DOMAIN_CPU, 0);
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for (offset = 0; offset < OBJECT_SIZE/4; offset++)
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igt_assert_eq(pass*OBJECT_SIZE/4 + offset, d[offset]);
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}
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for (i = 0; i < OBJECT_SIZE / CHUNK_SIZE; i++)
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gem_close(fd, batch[i].handle);
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free(batch);
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munmap(s, OBJECT_SIZE);
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gem_close(fd, src);
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munmap(d, OBJECT_SIZE);
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gem_close(fd, dst);
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}
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igt_main
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{
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int fd;
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igt_fixture
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fd = drm_open_any();
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igt_subtest("cpu")
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test_streaming(fd, 0);
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igt_subtest("gtt")
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test_streaming(fd, 1);
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igt_subtest("wc")
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test_streaming(fd, 2);
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igt_fixture
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close(fd);
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}
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