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tests: basic ring<->cpu and ring<->ring tests

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Using a dummy reloc that doesn't matter to trick the kernel into
synchroizing the rings.

v2: properly apply MI_NOOP workaround to MI_FLUSH_DW and
switch to MI_COND_BATCH_BUFFER_END as a dummy command on the
render ring to avoid PIPE_CONTROL errata.

v3: somebody clever decided that in C, you cound from 1,
i.e. I915_EXEC_RENDER == 1. It works now ...

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Daniel Vetter
2011-09-09 20:44:27 +02:00
parent 32f49c7c0d
commit 61b9806f4e
4 changed files with 341 additions and 0 deletions
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lib/intel_chipset.h
+4
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@@ -169,6 +169,10 @@
#define HAS_BLT_RING(devid) (IS_GEN6(devid) || \
IS_GEN7(devid))
#define HAS_BSD_RING(devid) (IS_GEN5(devid) || \
IS_GEN6(devid) || \
IS_GEN7(devid))
#define IS_BROADWATER(devid) (devid == PCI_CHIP_I946_GZ || \
devid == PCI_CHIP_I965_G_1 || \
devid == PCI_CHIP_I965_Q || \