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Add some initial definitions for Sandybridge.

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This commit is contained in:
Eric Anholt 2009-10-22 15:52:02 -07:00
parent c94174d106
commit 613d1c4896
2 changed files with 18 additions and 8 deletions
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16
lib/intel_chipset.h
View File

@ -70,6 +70,8 @@
#define PCI_CHIP_ILD_G 0x0042 #define PCI_CHIP_ILD_G 0x0042
#define PCI_CHIP_ILM_G 0x0046 #define PCI_CHIP_ILM_G 0x0046
#define PCI_CHIP_SANDYBRIDGE 0x0102
#define IS_MOBILE(devid) (devid == PCI_CHIP_I855_GM || \ #define IS_MOBILE(devid) (devid == PCI_CHIP_I855_GM || \
devid == PCI_CHIP_I915_GM || \ devid == PCI_CHIP_I915_GM || \
devid == PCI_CHIP_I945_GM || \ devid == PCI_CHIP_I945_GM || \
@ -100,15 +102,23 @@
devid == PCI_CHIP_Q33_G || \ devid == PCI_CHIP_Q33_G || \
devid == PCI_CHIP_Q35_G || IS_IGD(devid)) devid == PCI_CHIP_Q35_G || IS_IGD(devid))
#define IS_965(devid) (devid == PCI_CHIP_I965_G || \ #define IS_GEN4(devid) (devid == PCI_CHIP_I965_G || \
devid == PCI_CHIP_I965_Q || \ devid == PCI_CHIP_I965_Q || \
devid == PCI_CHIP_I965_G_1 || \ devid == PCI_CHIP_I965_G_1 || \
devid == PCI_CHIP_I965_GM || \ devid == PCI_CHIP_I965_GM || \
devid == PCI_CHIP_I965_GME || \ devid == PCI_CHIP_I965_GME || \
devid == PCI_CHIP_I946_GZ || \ devid == PCI_CHIP_I946_GZ || \
IS_G4X(devid) || \ IS_G4X(devid))
IS_IRONLAKE(devid))
#define IS_965(devid) (IS_GEN4(devid) || \
IS_IRONLAKE(devid) || \
IS_GEN6(devid))
#define IS_GEN6(devid) (devid == PCI_CHIP_SANDYBRIDGE)
#define IS_9XX(devid) (IS_915(devid) || \ #define IS_9XX(devid) (IS_915(devid) || \
IS_945(devid) || \ IS_945(devid) || \
IS_965(devid)) IS_965(devid))
#define HAS_PCH_SPLIT(devid) (IS_IRONLAKE(devid) || \
IS_GEN6(devid))

10
tools/intel_reg_dumper.c
View File

@ -131,7 +131,7 @@ DEBUGSTRING(i830_debug_dspcntr)
{ {
char *enabled = val & DISPLAY_PLANE_ENABLE ? "enabled" : "disabled"; char *enabled = val & DISPLAY_PLANE_ENABLE ? "enabled" : "disabled";
char plane = val & DISPPLANE_SEL_PIPE_B ? 'B' : 'A'; char plane = val & DISPPLANE_SEL_PIPE_B ? 'B' : 'A';
if (IS_IRONLAKE(devid)) if (HAS_PCH_SPLIT(devid))
asprintf(result, "%s", enabled); asprintf(result, "%s", enabled);
else else
asprintf(result, "%s, pipe %c", enabled, plane); asprintf(result, "%s, pipe %c", enabled, plane);
@ -149,7 +149,7 @@ DEBUGSTRING(i830_debug_pipeconf)
bit30 = bit30 =
val & PIPEACONF_DOUBLE_WIDE ? "double-wide" : "single-wide"; val & PIPEACONF_DOUBLE_WIDE ? "double-wide" : "single-wide";
if (IS_IRONLAKE(devid)) { if (HAS_PCH_SPLIT(devid)) {
switch (val & (7 << 5)) { switch (val & (7 << 5)) {
case PIPECONF_8BPP: case PIPECONF_8BPP:
bpc = "8bpc"; bpc = "8bpc";
@ -165,7 +165,7 @@ DEBUGSTRING(i830_debug_pipeconf)
break; break;
} }
} }
if (IS_IRONLAKE(devid)) if (HAS_PCH_SPLIT(devid))
asprintf(result, "%s, %s, %s", enabled, bit30, bpc); asprintf(result, "%s, %s, %s", enabled, bit30, bpc);
else else
asprintf(result, "%s, %s", enabled, bit30); asprintf(result, "%s, %s", enabled, bit30);
@ -447,7 +447,7 @@ DEBUGSTRING(i830_debug_adpa)
char hsync = (val & ADPA_HSYNC_ACTIVE_HIGH) ? '+' : '-'; char hsync = (val & ADPA_HSYNC_ACTIVE_HIGH) ? '+' : '-';
char vsync = (val & ADPA_VSYNC_ACTIVE_HIGH) ? '+' : '-'; char vsync = (val & ADPA_VSYNC_ACTIVE_HIGH) ? '+' : '-';
if (IS_IRONLAKE(devid)) if (HAS_PCH_SPLIT(devid))
asprintf(result, "%s, transcoder %c, %chsync, %cvsync", asprintf(result, "%s, transcoder %c, %chsync, %cvsync",
enable, pipe, hsync, vsync); enable, pipe, hsync, vsync);
else else
@ -1655,7 +1655,7 @@ int main(int argc, char** argv)
{ {
intel_get_mmio(); intel_get_mmio();
if (IS_IRONLAKE(devid)) if (HAS_PCH_SPLIT(devid))
ironlake_dump_regs(); ironlake_dump_regs();
else else
intel_dump_regs(); intel_dump_regs();