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https://github.com/tiagovignatti/intel-gpu-tools.git
synced 2026-08-20 04:42:53 +00:00
Add some initial definitions for Sandybridge.
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@@ -131,7 +131,7 @@ DEBUGSTRING(i830_debug_dspcntr)
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{
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char *enabled = val & DISPLAY_PLANE_ENABLE ? "enabled" : "disabled";
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char plane = val & DISPPLANE_SEL_PIPE_B ? 'B' : 'A';
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if (IS_IRONLAKE(devid))
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if (HAS_PCH_SPLIT(devid))
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asprintf(result, "%s", enabled);
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else
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asprintf(result, "%s, pipe %c", enabled, plane);
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@@ -149,7 +149,7 @@ DEBUGSTRING(i830_debug_pipeconf)
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bit30 =
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val & PIPEACONF_DOUBLE_WIDE ? "double-wide" : "single-wide";
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if (IS_IRONLAKE(devid)) {
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if (HAS_PCH_SPLIT(devid)) {
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switch (val & (7 << 5)) {
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case PIPECONF_8BPP:
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bpc = "8bpc";
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@@ -165,7 +165,7 @@ DEBUGSTRING(i830_debug_pipeconf)
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break;
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}
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}
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if (IS_IRONLAKE(devid))
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if (HAS_PCH_SPLIT(devid))
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asprintf(result, "%s, %s, %s", enabled, bit30, bpc);
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else
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asprintf(result, "%s, %s", enabled, bit30);
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@@ -447,7 +447,7 @@ DEBUGSTRING(i830_debug_adpa)
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char hsync = (val & ADPA_HSYNC_ACTIVE_HIGH) ? '+' : '-';
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char vsync = (val & ADPA_VSYNC_ACTIVE_HIGH) ? '+' : '-';
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if (IS_IRONLAKE(devid))
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if (HAS_PCH_SPLIT(devid))
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asprintf(result, "%s, transcoder %c, %chsync, %cvsync",
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enable, pipe, hsync, vsync);
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else
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@@ -1655,7 +1655,7 @@ int main(int argc, char** argv)
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{
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intel_get_mmio();
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if (IS_IRONLAKE(devid))
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if (HAS_PCH_SPLIT(devid))
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ironlake_dump_regs();
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else
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intel_dump_regs();
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