mirror of
https://github.com/tiagovignatti/intel-gpu-tools.git
synced 2025-06-11 01:46:14 +00:00
tools/intel_reg_dumper: fixup new warnings
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Daniel Vetter
parent
d50e6368ab
commit
5774fadf7d
@ -26,7 +26,6 @@
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*/
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#define _GNU_SOURCE
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#include <unistd.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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@ -44,7 +43,7 @@ DEBUGSTRING(i830_16bit_func)
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DEBUGSTRING(i830_debug_dcc)
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{
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char *addressing = NULL;
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const char *addressing = NULL;
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if (!IS_MOBILE(devid))
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return;
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@ -79,7 +78,7 @@ DEBUGSTRING(i830_debug_dcc)
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DEBUGSTRING(i830_debug_chdecmisc)
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{
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char *enhmodesel = NULL;
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const char *enhmodesel = NULL;
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switch ((val >> 5) & 3) {
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case 1:
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@ -131,7 +130,7 @@ DEBUGSTRING(i830_debug_dspstride)
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DEBUGSTRING(i830_debug_dspcntr)
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{
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char *enabled = val & DISPLAY_PLANE_ENABLE ? "enabled" : "disabled";
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const char *enabled = val & DISPLAY_PLANE_ENABLE ? "enabled" : "disabled";
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char plane = val & DISPPLANE_SEL_PIPE_B ? 'B' : 'A';
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if (HAS_PCH_SPLIT(devid))
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snprintf(result, len, "%s", enabled);
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@ -141,8 +140,8 @@ DEBUGSTRING(i830_debug_dspcntr)
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DEBUGSTRING(i830_debug_pipeconf)
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{
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char *enabled = val & PIPEACONF_ENABLE ? "enabled" : "disabled";
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char *bit30;
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const char *enabled = val & PIPEACONF_ENABLE ? "enabled" : "disabled";
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const char *bit30;
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if (IS_965(devid))
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bit30 = val & I965_PIPECONF_ACTIVE ? "active" : "inactive";
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@ -151,7 +150,7 @@ DEBUGSTRING(i830_debug_pipeconf)
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val & PIPEACONF_DOUBLE_WIDE ? "double-wide" : "single-wide";
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if (HAS_PCH_SPLIT(devid)) {
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char *bpc;
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const char *bpc;
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switch (val & (7 << 5)) {
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case PIPECONF_8BPP:
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@ -177,54 +176,54 @@ DEBUGSTRING(i830_debug_pipeconf)
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DEBUGSTRING(i830_debug_pipestat)
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{
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char *_FIFO_UNDERRUN = val & FIFO_UNDERRUN ? " FIFO_UNDERRUN" : "";
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char *_CRC_ERROR_ENABLE =
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const char *_FIFO_UNDERRUN = val & FIFO_UNDERRUN ? " FIFO_UNDERRUN" : "";
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const char *_CRC_ERROR_ENABLE =
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val & CRC_ERROR_ENABLE ? " CRC_ERROR_ENABLE" : "";
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char *_CRC_DONE_ENABLE =
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const char *_CRC_DONE_ENABLE =
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val & CRC_DONE_ENABLE ? " CRC_DONE_ENABLE" : "";
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char *_GMBUS_EVENT_ENABLE =
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const char *_GMBUS_EVENT_ENABLE =
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val & GMBUS_EVENT_ENABLE ? " GMBUS_EVENT_ENABLE" : "";
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char *_VSYNC_INT_ENABLE =
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const char *_VSYNC_INT_ENABLE =
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val & VSYNC_INT_ENABLE ? " VSYNC_INT_ENABLE" : "";
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char *_DLINE_COMPARE_ENABLE =
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const char *_DLINE_COMPARE_ENABLE =
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val & DLINE_COMPARE_ENABLE ? " DLINE_COMPARE_ENABLE" : "";
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char *_DPST_EVENT_ENABLE =
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const char *_DPST_EVENT_ENABLE =
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val & DPST_EVENT_ENABLE ? " DPST_EVENT_ENABLE" : "";
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char *_LBLC_EVENT_ENABLE =
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const char *_LBLC_EVENT_ENABLE =
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val & LBLC_EVENT_ENABLE ? " LBLC_EVENT_ENABLE" : "";
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char *_OFIELD_INT_ENABLE =
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const char *_OFIELD_INT_ENABLE =
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val & OFIELD_INT_ENABLE ? " OFIELD_INT_ENABLE" : "";
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char *_EFIELD_INT_ENABLE =
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const char *_EFIELD_INT_ENABLE =
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val & EFIELD_INT_ENABLE ? " EFIELD_INT_ENABLE" : "";
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char *_SVBLANK_INT_ENABLE =
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const char *_SVBLANK_INT_ENABLE =
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val & SVBLANK_INT_ENABLE ? " SVBLANK_INT_ENABLE" : "";
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char *_VBLANK_INT_ENABLE =
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const char *_VBLANK_INT_ENABLE =
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val & VBLANK_INT_ENABLE ? " VBLANK_INT_ENABLE" : "";
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char *_OREG_UPDATE_ENABLE =
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const char *_OREG_UPDATE_ENABLE =
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val & OREG_UPDATE_ENABLE ? " OREG_UPDATE_ENABLE" : "";
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char *_CRC_ERROR_INT_STATUS =
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const char *_CRC_ERROR_INT_STATUS =
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val & CRC_ERROR_INT_STATUS ? " CRC_ERROR_INT_STATUS" : "";
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char *_CRC_DONE_INT_STATUS =
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const char *_CRC_DONE_INT_STATUS =
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val & CRC_DONE_INT_STATUS ? " CRC_DONE_INT_STATUS" : "";
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char *_GMBUS_INT_STATUS =
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const char *_GMBUS_INT_STATUS =
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val & GMBUS_INT_STATUS ? " GMBUS_INT_STATUS" : "";
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char *_VSYNC_INT_STATUS =
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const char *_VSYNC_INT_STATUS =
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val & VSYNC_INT_STATUS ? " VSYNC_INT_STATUS" : "";
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char *_DLINE_COMPARE_STATUS =
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const char *_DLINE_COMPARE_STATUS =
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val & DLINE_COMPARE_STATUS ? " DLINE_COMPARE_STATUS" : "";
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char *_DPST_EVENT_STATUS =
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const char *_DPST_EVENT_STATUS =
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val & DPST_EVENT_STATUS ? " DPST_EVENT_STATUS" : "";
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char *_LBLC_EVENT_STATUS =
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const char *_LBLC_EVENT_STATUS =
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val & LBLC_EVENT_STATUS ? " LBLC_EVENT_STATUS" : "";
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char *_OFIELD_INT_STATUS =
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const char *_OFIELD_INT_STATUS =
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val & OFIELD_INT_STATUS ? " OFIELD_INT_STATUS" : "";
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char *_EFIELD_INT_STATUS =
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const char *_EFIELD_INT_STATUS =
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val & EFIELD_INT_STATUS ? " EFIELD_INT_STATUS" : "";
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char *_SVBLANK_INT_STATUS =
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const char *_SVBLANK_INT_STATUS =
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val & SVBLANK_INT_STATUS ? " SVBLANK_INT_STATUS" : "";
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char *_VBLANK_INT_STATUS =
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const char *_VBLANK_INT_STATUS =
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val & VBLANK_INT_STATUS ? " VBLANK_INT_STATUS" : "";
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char *_OREG_UPDATE_STATUS =
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const char *_OREG_UPDATE_STATUS =
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val & OREG_UPDATE_STATUS ? " OREG_UPDATE_STATUS" : "";
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snprintf(result, len,
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"status:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
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@ -257,7 +256,7 @@ DEBUGSTRING(i830_debug_pipestat)
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DEBUGSTRING(ivb_debug_port)
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{
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char *drrs;
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const char *drrs = NULL;
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switch (val & (2 << 30)) {
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case PORT_DBG_DRRS_HW_STATE_OFF:
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drrs = "off";
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@ -333,9 +332,9 @@ DEBUGSTRING(i830_debug_vga_pd)
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DEBUGSTRING(i830_debug_pp_status)
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{
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char *status = val & PP_ON ? "on" : "off";
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char *ready = val & PP_READY ? "ready" : "not ready";
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char *seq = "unknown";
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const char *status = val & PP_ON ? "on" : "off";
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const char *ready = val & PP_READY ? "ready" : "not ready";
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const char *seq = "unknown";
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switch (val & PP_SEQUENCE_MASK) {
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case PP_SEQUENCE_NONE:
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@ -360,12 +359,12 @@ DEBUGSTRING(i830_debug_pp_control)
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DEBUGSTRING(i830_debug_dpll)
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{
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char *enabled = val & DPLL_VCO_ENABLE ? "enabled" : "disabled";
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char *dvomode = val & DPLL_DVO_HIGH_SPEED ? "dvo" : "non-dvo";
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char *vgamode = val & DPLL_VGA_MODE_DIS ? "" : ", VGA";
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char *mode = "unknown";
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char *clock = "unknown";
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char *fpextra = val & DISPLAY_RATE_SELECT_FPA1 ? ", using FPx1!" : "";
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const char *enabled = val & DPLL_VCO_ENABLE ? "enabled" : "disabled";
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const char *dvomode = val & DPLL_DVO_HIGH_SPEED ? "dvo" : "non-dvo";
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const char *vgamode = val & DPLL_VGA_MODE_DIS ? "" : ", VGA";
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const char *mode = "unknown";
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const char *clock = "unknown";
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const char *fpextra = val & DISPLAY_RATE_SELECT_FPA1 ? ", using FPx1!" : "";
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char sdvoextra[20];
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int p1, p2 = 0;
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@ -448,13 +447,13 @@ DEBUGSTRING(i830_debug_dpll)
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DEBUGSTRING(i830_debug_dpll_test)
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{
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char *dpllandiv = val & DPLLA_TEST_N_BYPASS ? ", DPLLA N bypassed" : "";
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char *dpllamdiv = val & DPLLA_TEST_M_BYPASS ? ", DPLLA M bypassed" : "";
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char *dpllainput = val & DPLLA_INPUT_BUFFER_ENABLE ?
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const char *dpllandiv = val & DPLLA_TEST_N_BYPASS ? ", DPLLA N bypassed" : "";
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const char *dpllamdiv = val & DPLLA_TEST_M_BYPASS ? ", DPLLA M bypassed" : "";
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const char *dpllainput = val & DPLLA_INPUT_BUFFER_ENABLE ?
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"" : ", DPLLA input buffer disabled";
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char *dpllbndiv = val & DPLLB_TEST_N_BYPASS ? ", DPLLB N bypassed" : "";
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char *dpllbmdiv = val & DPLLB_TEST_M_BYPASS ? ", DPLLB M bypassed" : "";
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char *dpllbinput = val & DPLLB_INPUT_BUFFER_ENABLE ?
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const char *dpllbndiv = val & DPLLB_TEST_N_BYPASS ? ", DPLLB N bypassed" : "";
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const char *dpllbmdiv = val & DPLLB_TEST_M_BYPASS ? ", DPLLB M bypassed" : "";
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const char *dpllbinput = val & DPLLB_INPUT_BUFFER_ENABLE ?
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"" : ", DPLLB input buffer disabled";
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snprintf(result, len, "%s%s%s%s%s%s",
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@ -465,7 +464,7 @@ DEBUGSTRING(i830_debug_dpll_test)
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DEBUGSTRING(i830_debug_adpa)
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{
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char pipe = (val & ADPA_PIPE_B_SELECT) ? 'B' : 'A';
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char *enable = (val & ADPA_DAC_ENABLE) ? "enabled" : "disabled";
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const char *enable = (val & ADPA_DAC_ENABLE) ? "enabled" : "disabled";
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char hsync = (val & ADPA_HSYNC_ACTIVE_HIGH) ? '+' : '-';
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char vsync = (val & ADPA_VSYNC_ACTIVE_HIGH) ? '+' : '-';
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@ -483,9 +482,9 @@ DEBUGSTRING(i830_debug_adpa)
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DEBUGSTRING(i830_debug_lvds)
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{
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char pipe = val & LVDS_PIPEB_SELECT ? 'B' : 'A';
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char *enable = val & LVDS_PORT_EN ? "enabled" : "disabled";
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const char *enable = val & LVDS_PORT_EN ? "enabled" : "disabled";
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int depth;
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char *channels;
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const char *channels;
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if ((val & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
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depth = 24;
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@ -505,9 +504,9 @@ DEBUGSTRING(i830_debug_lvds)
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DEBUGSTRING(i830_debug_dvo)
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{
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char *enable = val & DVO_ENABLE ? "enabled" : "disabled";
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const char *enable = val & DVO_ENABLE ? "enabled" : "disabled";
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char pipe = val & DVO_PIPE_B_SELECT ? 'B' : 'A';
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char *stall;
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const char *stall;
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char hsync = val & DVO_HSYNC_ACTIVE_HIGH ? '+' : '-';
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char vsync = val & DVO_VSYNC_ACTIVE_HIGH ? '+' : '-';
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@ -532,11 +531,11 @@ DEBUGSTRING(i830_debug_dvo)
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DEBUGSTRING(i830_debug_sdvo)
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{
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char *enable = val & SDVO_ENABLE ? "enabled" : "disabled";
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const char *enable = val & SDVO_ENABLE ? "enabled" : "disabled";
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char pipe = val & SDVO_PIPE_B_SELECT ? 'B' : 'A';
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char *stall = val & SDVO_STALL_SELECT ? "enabled" : "disabled";
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char *detected = val & SDVO_DETECTED ? "" : "not ";
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char *gang = val & SDVOC_GANG_MODE ? ", gang mode" : "";
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const char *stall = val & SDVO_STALL_SELECT ? "enabled" : "disabled";
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const char *detected = val & SDVO_DETECTED ? "" : "not ";
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const char *gang = val & SDVOC_GANG_MODE ? ", gang mode" : "";
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char sdvoextra[20];
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if (IS_915(devid)) {
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@ -553,38 +552,38 @@ DEBUGSTRING(i830_debug_sdvo)
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DEBUGSTRING(i830_debug_dspclk_gate_d)
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{
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char *DPUNIT_B = val & DPUNIT_B_CLOCK_GATE_DISABLE ? " DPUNIT_B" : "";
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char *VSUNIT = val & VSUNIT_CLOCK_GATE_DISABLE ? " VSUNIT" : "";
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char *VRHUNIT = val & VRHUNIT_CLOCK_GATE_DISABLE ? " VRHUNIT" : "";
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char *VRDUNIT = val & VRDUNIT_CLOCK_GATE_DISABLE ? " VRDUNIT" : "";
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char *AUDUNIT = val & AUDUNIT_CLOCK_GATE_DISABLE ? " AUDUNIT" : "";
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char *DPUNIT_A = val & DPUNIT_A_CLOCK_GATE_DISABLE ? " DPUNIT_A" : "";
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char *DPCUNIT = val & DPCUNIT_CLOCK_GATE_DISABLE ? " DPCUNIT" : "";
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char *TVRUNIT = val & TVRUNIT_CLOCK_GATE_DISABLE ? " TVRUNIT" : "";
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char *TVCUNIT = val & TVCUNIT_CLOCK_GATE_DISABLE ? " TVCUNIT" : "";
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char *TVFUNIT = val & TVFUNIT_CLOCK_GATE_DISABLE ? " TVFUNIT" : "";
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char *TVEUNIT = val & TVEUNIT_CLOCK_GATE_DISABLE ? " TVEUNIT" : "";
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char *DVSUNIT = val & DVSUNIT_CLOCK_GATE_DISABLE ? " DVSUNIT" : "";
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char *DSSUNIT = val & DSSUNIT_CLOCK_GATE_DISABLE ? " DSSUNIT" : "";
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char *DDBUNIT = val & DDBUNIT_CLOCK_GATE_DISABLE ? " DDBUNIT" : "";
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char *DPRUNIT = val & DPRUNIT_CLOCK_GATE_DISABLE ? " DPRUNIT" : "";
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char *DPFUNIT = val & DPFUNIT_CLOCK_GATE_DISABLE ? " DPFUNIT" : "";
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char *DPBMUNIT = val & DPBMUNIT_CLOCK_GATE_DISABLE ? " DPBMUNIT" : "";
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char *DPLSUNIT = val & DPLSUNIT_CLOCK_GATE_DISABLE ? " DPLSUNIT" : "";
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char *DPLUNIT = val & DPLUNIT_CLOCK_GATE_DISABLE ? " DPLUNIT" : "";
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char *DPOUNIT = val & DPOUNIT_CLOCK_GATE_DISABLE ? " DPOUNIT" : "";
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char *DPBUNIT = val & DPBUNIT_CLOCK_GATE_DISABLE ? " DPBUNIT" : "";
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char *DCUNIT = val & DCUNIT_CLOCK_GATE_DISABLE ? " DCUNIT" : "";
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char *DPUNIT = val & DPUNIT_CLOCK_GATE_DISABLE ? " DPUNIT" : "";
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char *VRUNIT = val & VRUNIT_CLOCK_GATE_DISABLE ? " VRUNIT" : "";
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char *OVHUNIT = val & OVHUNIT_CLOCK_GATE_DISABLE ? " OVHUNIT" : "";
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char *DPIOUNIT = val & DPIOUNIT_CLOCK_GATE_DISABLE ? " DPIOUNIT" : "";
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char *OVFUNIT = val & OVFUNIT_CLOCK_GATE_DISABLE ? " OVFUNIT" : "";
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char *OVBUNIT = val & OVBUNIT_CLOCK_GATE_DISABLE ? " OVBUNIT" : "";
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char *OVRUNIT = val & OVRUNIT_CLOCK_GATE_DISABLE ? " OVRUNIT" : "";
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char *OVCUNIT = val & OVCUNIT_CLOCK_GATE_DISABLE ? " OVCUNIT" : "";
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char *OVUUNIT = val & OVUUNIT_CLOCK_GATE_DISABLE ? " OVUUNIT" : "";
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char *OVLUNIT = val & OVLUNIT_CLOCK_GATE_DISABLE ? " OVLUNIT" : "";
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const char *DPUNIT_B = val & DPUNIT_B_CLOCK_GATE_DISABLE ? " DPUNIT_B" : "";
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const char *VSUNIT = val & VSUNIT_CLOCK_GATE_DISABLE ? " VSUNIT" : "";
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const char *VRHUNIT = val & VRHUNIT_CLOCK_GATE_DISABLE ? " VRHUNIT" : "";
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const char *VRDUNIT = val & VRDUNIT_CLOCK_GATE_DISABLE ? " VRDUNIT" : "";
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const char *AUDUNIT = val & AUDUNIT_CLOCK_GATE_DISABLE ? " AUDUNIT" : "";
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const char *DPUNIT_A = val & DPUNIT_A_CLOCK_GATE_DISABLE ? " DPUNIT_A" : "";
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const char *DPCUNIT = val & DPCUNIT_CLOCK_GATE_DISABLE ? " DPCUNIT" : "";
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const char *TVRUNIT = val & TVRUNIT_CLOCK_GATE_DISABLE ? " TVRUNIT" : "";
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const char *TVCUNIT = val & TVCUNIT_CLOCK_GATE_DISABLE ? " TVCUNIT" : "";
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const char *TVFUNIT = val & TVFUNIT_CLOCK_GATE_DISABLE ? " TVFUNIT" : "";
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const char *TVEUNIT = val & TVEUNIT_CLOCK_GATE_DISABLE ? " TVEUNIT" : "";
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const char *DVSUNIT = val & DVSUNIT_CLOCK_GATE_DISABLE ? " DVSUNIT" : "";
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const char *DSSUNIT = val & DSSUNIT_CLOCK_GATE_DISABLE ? " DSSUNIT" : "";
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const char *DDBUNIT = val & DDBUNIT_CLOCK_GATE_DISABLE ? " DDBUNIT" : "";
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const char *DPRUNIT = val & DPRUNIT_CLOCK_GATE_DISABLE ? " DPRUNIT" : "";
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const char *DPFUNIT = val & DPFUNIT_CLOCK_GATE_DISABLE ? " DPFUNIT" : "";
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const char *DPBMUNIT = val & DPBMUNIT_CLOCK_GATE_DISABLE ? " DPBMUNIT" : "";
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const char *DPLSUNIT = val & DPLSUNIT_CLOCK_GATE_DISABLE ? " DPLSUNIT" : "";
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const char *DPLUNIT = val & DPLUNIT_CLOCK_GATE_DISABLE ? " DPLUNIT" : "";
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const char *DPOUNIT = val & DPOUNIT_CLOCK_GATE_DISABLE ? " DPOUNIT" : "";
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const char *DPBUNIT = val & DPBUNIT_CLOCK_GATE_DISABLE ? " DPBUNIT" : "";
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const char *DCUNIT = val & DCUNIT_CLOCK_GATE_DISABLE ? " DCUNIT" : "";
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const char *DPUNIT = val & DPUNIT_CLOCK_GATE_DISABLE ? " DPUNIT" : "";
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const char *VRUNIT = val & VRUNIT_CLOCK_GATE_DISABLE ? " VRUNIT" : "";
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const char *OVHUNIT = val & OVHUNIT_CLOCK_GATE_DISABLE ? " OVHUNIT" : "";
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const char *DPIOUNIT = val & DPIOUNIT_CLOCK_GATE_DISABLE ? " DPIOUNIT" : "";
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const char *OVFUNIT = val & OVFUNIT_CLOCK_GATE_DISABLE ? " OVFUNIT" : "";
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const char *OVBUNIT = val & OVBUNIT_CLOCK_GATE_DISABLE ? " OVBUNIT" : "";
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const char *OVRUNIT = val & OVRUNIT_CLOCK_GATE_DISABLE ? " OVRUNIT" : "";
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const char *OVCUNIT = val & OVCUNIT_CLOCK_GATE_DISABLE ? " OVCUNIT" : "";
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const char *OVUUNIT = val & OVUUNIT_CLOCK_GATE_DISABLE ? " OVUUNIT" : "";
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const char *OVLUNIT = val & OVLUNIT_CLOCK_GATE_DISABLE ? " OVLUNIT" : "";
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snprintf(result, len,
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"clock gates disabled:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
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@ -618,7 +617,7 @@ DEBUGSTRING(i810_debug_915_fence)
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DEBUGSTRING(i810_debug_965_fence_start)
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{
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char *enable = (val & FENCE_VALID) ? " enabled" : "disabled";
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const char *enable = (val & FENCE_VALID) ? " enabled" : "disabled";
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||||
char format = (val & I965_FENCE_Y_MAJOR) ? 'Y' : 'X';
|
||||
int pitch = ((val & 0xffc) >> 2) * 128 + 128;
|
||||
unsigned int offset = val & 0xfffff000;
|
||||
@ -649,7 +648,7 @@ DEBUGSTRING(i810_debug_965_fence_end)
|
||||
|
||||
struct reg_debug {
|
||||
int reg;
|
||||
char *name;
|
||||
const char *name;
|
||||
void (*debug_output) (char *result, int len, int reg, uint32_t val);
|
||||
uint32_t val;
|
||||
};
|
||||
@ -930,7 +929,7 @@ DEBUGSTRING(ironlake_debug_n)
|
||||
|
||||
DEBUGSTRING(ironlake_debug_fdi_tx_ctl)
|
||||
{
|
||||
char *train = NULL, *voltage = NULL, *pre_emphasis = NULL, *portw =
|
||||
const char *train = NULL, *voltage = NULL, *pre_emphasis = NULL, *portw =
|
||||
NULL;
|
||||
|
||||
switch (val & FDI_LINK_TRAIN_NONE) {
|
||||
@ -1035,7 +1034,7 @@ DEBUGSTRING(ironlake_debug_fdi_tx_ctl)
|
||||
|
||||
DEBUGSTRING(ironlake_debug_fdi_rx_ctl)
|
||||
{
|
||||
char *train = NULL, *portw = NULL, *bpc = NULL;
|
||||
const char *train = NULL, *portw = NULL, *bpc = NULL;
|
||||
|
||||
if (HAS_CPT) {
|
||||
switch (val & FDI_LINK_TRAIN_PATTERN_MASK_CPT) {
|
||||
@ -1124,12 +1123,12 @@ DEBUGSTRING(ironlake_debug_dspstride)
|
||||
|
||||
DEBUGSTRING(ironlake_debug_pch_dpll)
|
||||
{
|
||||
char *enable = val & DPLL_VCO_ENABLE ? "enable" : "disable";
|
||||
char *highspeed = val & DPLL_DVO_HIGH_SPEED ? "yes" : "no";
|
||||
char *mode = NULL;
|
||||
char *p2 = NULL;
|
||||
const char *enable = val & DPLL_VCO_ENABLE ? "enable" : "disable";
|
||||
const char *highspeed = val & DPLL_DVO_HIGH_SPEED ? "yes" : "no";
|
||||
const char *mode = NULL;
|
||||
const char *p2 = NULL;
|
||||
int fpa0_p1, fpa1_p1;
|
||||
char *refclk = NULL;
|
||||
const char *refclk = NULL;
|
||||
int sdvo_mul;
|
||||
|
||||
if ((val & DPLLB_MODE_LVDS) == DPLLB_MODE_LVDS) {
|
||||
@ -1176,16 +1175,16 @@ DEBUGSTRING(ironlake_debug_pch_dpll)
|
||||
|
||||
DEBUGSTRING(ironlake_debug_dref_ctl)
|
||||
{
|
||||
char *cpu_source;
|
||||
char *ssc_source = val & DREF_SSC_SOURCE_ENABLE ? "enable" : "disable";
|
||||
char *nonspread_source =
|
||||
const char *cpu_source;
|
||||
const char *ssc_source = val & DREF_SSC_SOURCE_ENABLE ? "enable" : "disable";
|
||||
const char *nonspread_source =
|
||||
val & DREF_NONSPREAD_SOURCE_ENABLE ? "enable" : "disable";
|
||||
char *superspread_source =
|
||||
const char *superspread_source =
|
||||
val & DREF_SUPERSPREAD_SOURCE_ENABLE ? "enable" : "disable";
|
||||
char *ssc4_mode =
|
||||
const char *ssc4_mode =
|
||||
val & DREF_SSC4_CENTERSPREAD ? "centerspread" : "downspread";
|
||||
char *ssc1 = val & DREF_SSC1_ENABLE ? "enable" : "disable";
|
||||
char *ssc4 = val & DREF_SSC4_ENABLE ? "enable" : "disable";
|
||||
const char *ssc1 = val & DREF_SSC1_ENABLE ? "enable" : "disable";
|
||||
const char *ssc4 = val & DREF_SSC4_ENABLE ? "enable" : "disable";
|
||||
|
||||
switch (val & DREF_CPU_SOURCE_OUTPUT_NONSPREAD) {
|
||||
case DREF_CPU_SOURCE_OUTPUT_DISABLE:
|
||||
@ -1208,7 +1207,7 @@ DEBUGSTRING(ironlake_debug_dref_ctl)
|
||||
|
||||
DEBUGSTRING(ironlake_debug_rawclk_freq)
|
||||
{
|
||||
char *tp1 = NULL, *tp2 = NULL;
|
||||
const char *tp1 = NULL, *tp2 = NULL;
|
||||
|
||||
switch (val & FDL_TP1_TIMER_MASK) {
|
||||
case 0:
|
||||
@ -1257,7 +1256,7 @@ DEBUGSTRING(ironlake_debug_transconf)
|
||||
|
||||
DEBUGSTRING(ironlake_debug_panel_fitting)
|
||||
{
|
||||
char *vadapt = NULL, *filter_sel = NULL;
|
||||
const char *vadapt = NULL, *filter_sel = NULL;
|
||||
|
||||
switch (val & (3 << 25)) {
|
||||
case 0:
|
||||
@ -1338,8 +1337,8 @@ DEBUGSTRING(ironlake_debug_pf_win)
|
||||
DEBUGSTRING(ironlake_debug_hdmi)
|
||||
{
|
||||
int pipe;
|
||||
char *enable, *bpc = NULL, *encoding;
|
||||
char *mode, *audio, *vsync, *hsync, *detect;
|
||||
const char *enable, *bpc = NULL, *encoding;
|
||||
const char *mode, *audio, *vsync, *hsync, *detect;
|
||||
|
||||
if (val & PORT_ENABLE)
|
||||
enable = "enabled";
|
||||
@ -1396,8 +1395,8 @@ DEBUGSTRING(ironlake_debug_hdmi)
|
||||
|
||||
DEBUGSTRING(snb_debug_dpll_sel)
|
||||
{
|
||||
char *transa, *transb;
|
||||
char *dplla = NULL, *dpllb = NULL;
|
||||
const char *transa, *transb;
|
||||
const char *dplla = NULL, *dpllb = NULL;
|
||||
|
||||
if (!HAS_CPT)
|
||||
return;
|
||||
@ -1426,7 +1425,7 @@ DEBUGSTRING(snb_debug_dpll_sel)
|
||||
|
||||
DEBUGSTRING(snb_debug_trans_dp_ctl)
|
||||
{
|
||||
char *enable, *port = NULL, *bpc = NULL, *vsync, *hsync;
|
||||
const char *enable, *port = NULL, *bpc = NULL, *vsync, *hsync;
|
||||
|
||||
if (!HAS_CPT)
|
||||
return;
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user