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https://github.com/tiagovignatti/intel-gpu-tools.git
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Fix up sampler send message translation and give it a near-usable syntax.
This commit is contained in:
parent
e609d6ba93
commit
56c4ccfc19
104
assembler/gram.y
104
assembler/gram.y
@ -58,8 +58,8 @@
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%token DOT
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%token DOT
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%token MINUS ABS
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%token MINUS ABS
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%token TYPE_UD, TYPE_D, TYPE_UW, TYPE_W, TYPE_UB, TYPE_B,
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%token <integer> TYPE_UD, TYPE_D, TYPE_UW, TYPE_W, TYPE_UB, TYPE_B,
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%token TYPE_VF, TYPE_HF, TYPE_V, TYPE_F
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%token <integer> TYPE_VF, TYPE_HF, TYPE_V, TYPE_F
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%token <integer> ALIGN1 ALIGN16 MASK_DISABLE EOT
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%token <integer> ALIGN1 ALIGN16 MASK_DISABLE EOT
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@ -82,14 +82,14 @@
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%type <instruction> specialinstruction
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%type <instruction> specialinstruction
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%type <instruction> dst dstoperand dstoperandex dstreg
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%type <instruction> dst dstoperand dstoperandex dstreg
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%type <instruction> directsrcaccoperand src directsrcoperand srcimm imm32reg
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%type <instruction> directsrcaccoperand src directsrcoperand srcimm imm32reg
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%type <instruction> srcacc srcaccimm
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%type <instruction> srcacc srcaccimm payload post_dst msgtarget
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%type <instruction> instoptions instoption_list
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%type <instruction> instoptions instoption_list
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%type <program> instrseq
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%type <program> instrseq
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%type <integer> instoption
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%type <integer> instoption
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%type <integer> unaryop binaryop binaryaccop
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%type <integer> unaryop binaryop binaryaccop
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%type <integer> conditionalmodifier saturate negate abs
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%type <integer> conditionalmodifier saturate negate abs
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%type <integer> regtype srcimmtype execsize dstregion
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%type <integer> regtype srcimmtype execsize dstregion
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%type <integer> subregnum msgtarget
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%type <integer> subregnum sampler_datatype
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%type <region> region
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%type <region> region
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%type <direct_gen_reg> directgenreg directmsgreg addrreg accreg flagreg maskreg
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%type <direct_gen_reg> directgenreg directmsgreg addrreg accreg flagreg maskreg
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%type <direct_gen_reg> nullreg
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%type <direct_gen_reg> nullreg
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@ -196,14 +196,31 @@ binaryaccop: ADD { $$ = BRW_OPCODE_ADD; }
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triinstruction: sendinstruction
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triinstruction: sendinstruction
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/* XXX formatting of this instruction */
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sendinstruction: predicate SEND execsize INTEGER post_dst payload msgtarget
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sendinstruction: predicate SEND INTEGER execsize dst payload msgtarget
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MSGLEN INTEGER RETURNLEN INTEGER instoptions
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MSGLEN INTEGER RETURNLEN INTEGER instoptions
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{
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{
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/* Send instructions are messy. The first argument is the
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* post destination -- the grf register that the response
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* starts from. The second argument is the current
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* destination, which is the start of the message arguments
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* to the shared function, and where src0 payload is loaded
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* to if not null. The payload is typically based on the
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* grf 0 thread payload of your current thread, and is
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* implicitly loaded if non-null.
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*/
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bzero(&$$, sizeof($$));
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bzero(&$$, sizeof($$));
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$$.header.opcode = BRW_OPCODE_SEND;
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$$.header.opcode = BRW_OPCODE_SEND;
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$$.header.execution_size = $4;
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$$.header.execution_size = $3;
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$$.header.destreg__conditionalmod = $3;
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$$.header.destreg__conditionalmod = $4; /* msg reg index */
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set_instruction_dest(&$$, &$5);
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set_instruction_src0(&$$, &$6);
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$$.bits1.da1.src1_reg_file = BRW_IMMEDIATE_VALUE;
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$$.bits1.da1.src1_reg_type = BRW_REGISTER_TYPE_D;
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$$.bits3.generic = $7.bits3.generic;
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$$.bits3.generic.msg_length = $9;
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$$.bits3.generic.response_length = $11;
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$$.bits3.generic.end_of_thread =
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$12.bits3.generic.msg_target;
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}
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}
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specialinstruction: NOP
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specialinstruction: NOP
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@ -216,16 +233,68 @@ specialinstruction: NOP
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payload: directsrcoperand
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payload: directsrcoperand
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;
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;
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msgtarget: NULL_TOKEN { $$ = BRW_MESSAGE_TARGET_NULL; }
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post_dst: dst
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| SAMPLER { $$ = BRW_MESSAGE_TARGET_SAMPLER; }
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| MATH { $$ = BRW_MESSAGE_TARGET_MATH; }
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| GATEWAY { $$ = BRW_MESSAGE_TARGET_GATEWAY; }
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| READ { $$ = BRW_MESSAGE_TARGET_DATAPORT_READ; }
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| WRITE { $$ = BRW_MESSAGE_TARGET_DATAPORT_WRITE; }
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| URB { $$ = BRW_MESSAGE_TARGET_URB; }
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| THREAD_SPAWNER { $$ = BRW_MESSAGE_TARGET_THREAD_SPAWNER; }
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;
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;
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msgtarget: NULL_TOKEN
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{
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$$.bits3.generic.msg_target = BRW_MESSAGE_TARGET_NULL;
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}
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| SAMPLER LPAREN INTEGER COMMA INTEGER COMMA
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sampler_datatype RPAREN
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{
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$$.bits3.generic.msg_target = BRW_MESSAGE_TARGET_SAMPLER;
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$$.bits3.sampler.binding_table_index = $3;
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$$.bits3.sampler.sampler = $5;
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switch ($7) {
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case TYPE_F:
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$$.bits3.sampler.return_format =
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BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
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break;
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case TYPE_UD:
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$$.bits3.sampler.return_format =
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BRW_SAMPLER_RETURN_FORMAT_UINT32;
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break;
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case TYPE_D:
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$$.bits3.sampler.return_format =
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BRW_SAMPLER_RETURN_FORMAT_SINT32;
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break;
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}
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}
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| MATH
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{
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$$.bits3.generic.msg_target = BRW_MESSAGE_TARGET_MATH;
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}
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| GATEWAY
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{
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$$.bits3.generic.msg_target = BRW_MESSAGE_TARGET_GATEWAY;
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}
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| READ
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{
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$$.bits3.generic.msg_target =
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BRW_MESSAGE_TARGET_DATAPORT_READ;
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}
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| WRITE
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{
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$$.bits3.generic.msg_target =
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BRW_MESSAGE_TARGET_DATAPORT_WRITE;
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}
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| URB
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{
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$$.bits3.generic.msg_target = BRW_MESSAGE_TARGET_URB;
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}
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| THREAD_SPAWNER
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{
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$$.bits3.generic.msg_target =
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BRW_MESSAGE_TARGET_THREAD_SPAWNER;
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}
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;
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sampler_datatype:
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TYPE_F
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| TYPE_UD
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| TYPE_D
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/* 1.4.2: Destination register */
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/* 1.4.2: Destination register */
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dst: dstoperand | dstoperandex
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dst: dstoperand | dstoperandex
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@ -511,7 +580,8 @@ instoption_list: instoption instoption_list
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$$.header.mask_control = BRW_MASK_DISABLE;
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$$.header.mask_control = BRW_MASK_DISABLE;
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break;
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break;
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case EOT:
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case EOT:
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/* XXX: EOT shouldn't be here */
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/* XXX: EOT shouldn't be an instoption, I don't think */
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$$.bits3.generic.end_of_thread = 1;
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break;
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break;
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}
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}
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}
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}
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@ -89,7 +89,7 @@ mov (8) m4<1>F g7<8,8,1>F { align1 };
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* g0 holds the PS thread payload, which (oddly) contains
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* g0 holds the PS thread payload, which (oddly) contains
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* precisely what the sampler wants to see in m0
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* precisely what the sampler wants to see in m0
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*/
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*/
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send 0 (16) g12<1>UW g0<8,8,1>UW sampler mlen 5 rlen 8 { align1 };
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send (16) 0 g12<1>UW g0<8,8,1>UW sampler (1,0,F) mlen 5 rlen 8 { align1 };
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mov (8) g19<1>UW g19<8,8,1>UW { align1 };
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mov (8) g19<1>UW g19<8,8,1>UW { align1 };
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/* color space conversion function:
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/* color space conversion function:
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@ -144,7 +144,7 @@ mac.sat (8) m8<1>F g15<8,8,1>F 1F { align1 };
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*/
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*/
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mov (8) m1<1>UD g1<8,8,1>UD { align1 mask_disable };
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mov (8) m1<1>UD g1<8,8,1>UD { align1 mask_disable };
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/* Send framebuffer write message: XXX: acc0? */
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/* Send framebuffer write message: XXX: acc0? */
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send 0 (16) null g0<8,8,1>UW write mlen 10 rlen 0 { align1 EOT };
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send (16) 0 null g0<8,8,1>UW write mlen 10 rlen 0 { align1 EOT };
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/* padding */
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/* padding */
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nop;
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nop;
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nop;
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nop;
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