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lib/ioctl_wrappers: Add gem_gtt_type exposing raw HAS_ALIASING_PPGTT param
No functional changes.
While I'm here, let's also rename gem_uses_aliasing_ppgtt (since it's
being used to indicate if we are using ANY kind of ppgtt) and introduce
gem_uses_full_ppgtt to drop some unnecessary code from tests that were
previously calling getparam directly instead of using ioctl wrapper.
v2: drop gem_uses_full_48b_ppgtt since it's no longer used anywhere,
s/48b/64b (Chris)
v3: rebase
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
committed by
Daniel Vetter
parent
0e2071411a
commit
52b5d5016e
+1
-1
@@ -358,7 +358,7 @@ static bool uses_cmd_parser(int fd, int gen)
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if (rc || parser_version == 0)
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return false;
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if (!gem_uses_aliasing_ppgtt(fd))
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if (!gem_uses_ppgtt(fd))
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return false;
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if (gen != 7)
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+1
-10
@@ -46,16 +46,7 @@ IGT_TEST_DESCRIPTION("Simulates SNA behaviour using negative self-relocations"
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static uint64_t get_page_table_size(int fd)
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{
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struct drm_i915_getparam gp;
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int val = 0;
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memset(&gp, 0, sizeof(gp));
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gp.param = 18; /* HAS_ALIASING_PPGTT */
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gp.value = &val;
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if (drmIoctl(fd, DRM_IOCTL_I915_GETPARAM, &gp))
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return 0;
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errno = 0;
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int val = gem_gtt_type(fd);
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switch (val) {
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case 0:
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+2
-18
@@ -117,22 +117,6 @@ static void *thread(void *bufmgr)
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return NULL;
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}
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static int uses_ppgtt(int _fd)
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{
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struct drm_i915_getparam gp;
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int val = 0;
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memset(&gp, 0, sizeof(gp));
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gp.param = 18; /* HAS_ALIASING_PPGTT */
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gp.value = &val;
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if (drmIoctl(_fd, DRM_IOCTL_I915_GETPARAM, &gp))
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return 0;
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errno = 0;
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return val;
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}
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static void
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processes(void)
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{
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@@ -150,7 +134,7 @@ processes(void)
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devid = intel_get_drm_devid(fd);
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aperture = gem_aperture_size(fd);
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ppgtt_mode = uses_ppgtt(fd);
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ppgtt_mode = gem_gtt_type(fd);
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igt_require(ppgtt_mode);
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render_copy = igt_get_render_copyfunc(devid);
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@@ -252,7 +236,7 @@ threads(void)
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devid = intel_get_drm_devid(fd);
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aperture = gem_aperture_size(fd);
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ppgtt_mode = uses_ppgtt(fd);
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ppgtt_mode = gem_gtt_type(fd);
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igt_require(ppgtt_mode);
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render_copy = igt_get_render_copyfunc(devid);
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@@ -306,7 +306,7 @@ igt_main
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rc = drmIoctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
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igt_require(!rc && parser_version > 0);
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igt_require(gem_uses_aliasing_ppgtt(fd));
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igt_require(gem_uses_ppgtt(fd));
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handle = gem_create(fd, 4096);
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+2
-18
@@ -44,22 +44,6 @@
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#define HEIGHT 512
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#define SIZE (HEIGHT*STRIDE)
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static bool uses_full_ppgtt(int fd)
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{
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struct drm_i915_getparam gp;
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int val = 0;
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memset(&gp, 0, sizeof(gp));
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gp.param = 18; /* HAS_ALIASING_PPGTT */
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gp.value = &val;
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if (drmIoctl(fd, DRM_IOCTL_I915_GETPARAM, &gp))
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return 0;
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errno = 0;
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return val > 1;
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}
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static drm_intel_bo *create_bo(drm_intel_bufmgr *bufmgr,
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uint32_t pixel)
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{
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@@ -240,7 +224,7 @@ static void flink_and_close(void)
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uint64_t offset, offset_new;
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fd = drm_open_driver(DRIVER_INTEL);
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igt_require(uses_full_ppgtt(fd));
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igt_require(gem_uses_full_ppgtt(fd));
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bo = gem_create(fd, 4096);
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name = gem_flink(fd, bo);
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@@ -277,7 +261,7 @@ static void flink_and_exit(void)
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const int retries = 50;
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fd = drm_open_driver(DRIVER_INTEL);
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igt_require(uses_full_ppgtt(fd));
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igt_require(gem_uses_full_ppgtt(fd));
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bo = gem_create(fd, 4096);
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name = gem_flink(fd, bo);
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+1
-1
@@ -322,7 +322,7 @@ static void test_evict_snoop(int fd)
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uint64_t hole;
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igt_require(!gem_has_llc(fd));
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igt_require(!gem_uses_aliasing_ppgtt(fd));
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igt_require(!gem_uses_ppgtt(fd));
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memset(&execbuf, 0, sizeof(execbuf));
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execbuf.buffers_ptr = (uintptr_t)object;
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@@ -136,7 +136,7 @@ igt_main
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fd = drm_open_driver(DRIVER_INTEL);
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devid = intel_get_drm_devid(fd);
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has_ppgtt = gem_uses_aliasing_ppgtt(fd);
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has_ppgtt = gem_uses_ppgtt(fd);
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/* storedw needs gtt address on gen4+/g33 and snoopable memory.
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* Strictly speaking we could implement this now ... */
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@@ -189,7 +189,7 @@ igt_main
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"needs snoopable mem on pre-gen6\n");
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/* This only works with ppgtt */
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igt_require(gem_uses_aliasing_ppgtt(fd));
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igt_require(gem_uses_ppgtt(fd));
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}
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for (i = 0; i < ARRAY_SIZE(rings); i++) {
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+1
-1
@@ -288,7 +288,7 @@ static void load_helper_stop(void)
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static void load_helper_init(void)
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{
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lh.devid = intel_get_drm_devid(drm_fd);
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lh.has_ppgtt = gem_uses_aliasing_ppgtt(drm_fd);
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lh.has_ppgtt = gem_uses_ppgtt(drm_fd);
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/* MI_STORE_DATA can only use GTT address on gen4+/g33 and needs
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* snoopable mem on pre-gen6. Hence load-helper only works on gen6+, but
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+1
-1
@@ -258,7 +258,7 @@ gem_init(void)
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gem.gen = intel_gen(gem.devid);
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igt_require_f(gem.gen >= 8,
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"SSEU power gating only relevant for Gen8+");
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gem.has_ppgtt = gem_uses_aliasing_ppgtt(gem.drm_fd);
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gem.has_ppgtt = gem_uses_ppgtt(gem.drm_fd);
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gem.bufmgr = drm_intel_bufmgr_gem_init(gem.drm_fd, 4096);
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igt_assert(gem.bufmgr);
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