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https://github.com/tiagovignatti/intel-gpu-tools.git
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Support src ARF operands in another place, and spell it arch instead of acc.
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commit
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@ -91,7 +91,7 @@
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%type <instruction> binaryaccinstruction triinstruction sendinstruction
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%type <instruction> binaryaccinstruction triinstruction sendinstruction
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%type <instruction> specialinstruction
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%type <instruction> specialinstruction
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%type <instruction> dst dstoperand dstoperandex dstreg
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%type <instruction> dst dstoperand dstoperandex dstreg
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%type <instruction> directsrcaccoperand srcaccoperandex src directsrcoperand
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%type <instruction> directsrcaccoperand srcarchoperandex src directsrcoperand
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%type <instruction> srcimm imm32reg
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%type <instruction> srcimm imm32reg
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%type <instruction> srcacc srcaccimm payload post_dst msgtarget
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%type <instruction> srcacc srcaccimm payload post_dst msgtarget
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%type <instruction> instoptions instoption_list
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%type <instruction> instoptions instoption_list
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@ -107,7 +107,7 @@
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%type <direct_gen_reg> directgenreg directmsgreg addrreg accreg flagreg maskreg
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%type <direct_gen_reg> directgenreg directmsgreg addrreg accreg flagreg maskreg
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%type <direct_gen_reg> maskstackreg maskstackdepthreg notifyreg
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%type <direct_gen_reg> maskstackreg maskstackdepthreg notifyreg
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%type <direct_gen_reg> statereg controlreg ipreg nullreg
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%type <direct_gen_reg> statereg controlreg ipreg nullreg
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%type <direct_gen_reg> dstoperandex_typed srcaccoperandex_typed
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%type <direct_gen_reg> dstoperandex_typed srcarchoperandex_typed
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%type <integer> mask_subreg maskstack_subreg maskstackdepth_subreg
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%type <integer> mask_subreg maskstack_subreg maskstackdepth_subreg
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%type <imm32> imm32
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%type <imm32> imm32
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@ -499,11 +499,11 @@ imm32reg: imm32 srcimmtype
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;
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;
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/* XXX: accreg regtype */
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/* XXX: accreg regtype */
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directsrcaccoperand: directsrcoperand | srcaccoperandex
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directsrcaccoperand: directsrcoperand
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;
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;
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/* Returns a source operand in the src0 fields of an instruction. */
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/* Returns a source operand in the src0 fields of an instruction. */
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srcaccoperandex: srcaccoperandex_typed region regtype
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srcarchoperandex: srcarchoperandex_typed region regtype
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{
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{
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$$.bits1.da1.src0_reg_file = $1.reg_file;
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$$.bits1.da1.src0_reg_file = $1.reg_file;
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$$.bits1.da1.src0_reg_type = $3;
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$$.bits1.da1.src0_reg_type = $3;
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@ -541,14 +541,13 @@ srcaccoperandex: srcaccoperandex_typed region regtype
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}
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}
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;
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;
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srcaccoperandex_typed: flagreg | addrreg | maskreg
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srcarchoperandex_typed: flagreg | addrreg | maskreg
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;
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;
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/* XXX: indirectsrcoperand */
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/* XXX: indirectsrcoperand */
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src: directsrcoperand
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src: directsrcoperand
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;
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;
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/* XXX: srcaccoperandex */
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directsrcoperand:
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directsrcoperand:
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negate abs directgenreg region regtype
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negate abs directgenreg region regtype
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{
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{
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@ -565,6 +564,7 @@ directsrcoperand:
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$$.bits2.da1.src0_negate = $1;
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$$.bits2.da1.src0_negate = $1;
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$$.bits2.da1.src0_abs = $2;
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$$.bits2.da1.src0_abs = $2;
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}
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}
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| srcarchoperandex
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;
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;
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subregnum: DOT INTEGER
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subregnum: DOT INTEGER
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