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tests/gem_pipe_control_store_loop: Add subtest for reused buffers
This exercises the slightly faulty kernel w/a that Eric fixed in commit e844b990b1df9242bb91b7d490552f3198946838 Author: Eric Anholt <eric@anholt.net> Date: Tue Jul 31 15:35:01 2012 -0700 drm/i915: Don't forget to apply SNB PIPE_CONTROL GTT workaround. If a buffer that was the target of a PIPE_CONTROL from userland was a reused one that hadn't been evicted which had not previously had this workaround applied, then the early return for a correct presumed_offset in this function meant we would not bind it into the GTT and the write would land somewhere else. Fixes reproducible failures with GL_EXT_timer_query usage in apitrace, and I also expect it to fix the intermittent OQ issues on snb that danvet's been working on. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=48019 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=52932 Signed-off-by: Eric Anholt <eric@anholt.net> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Carl Worth <cworth@cworth.org> Tested-by: Carl Worth <cworth@cworth.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -63,7 +63,7 @@ uint32_t devid;
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/* Like the store dword test, but we create new command buffers each time */
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static void
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store_pipe_control_loop(void)
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store_pipe_control_loop(bool preuse_buffer)
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{
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int i, val = 0;
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uint32_t *buf;
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@ -78,6 +78,29 @@ store_pipe_control_loop(void)
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igt_fail(-1);
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}
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if (preuse_buffer) {
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BEGIN_BATCH(6);
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OUT_BATCH(XY_COLOR_BLT_CMD | COLOR_BLT_WRITE_ALPHA | XY_COLOR_BLT_WRITE_RGB);
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OUT_BATCH((3 << 24) | (0xf0 << 16) | 64);
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OUT_BATCH(0);
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OUT_BATCH(1 << 16 | 1);
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/*
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* IMPORTANT: We need to preuse the buffer in a
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* different domain than what the pipe control write
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* (and kernel wa) uses!
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*/
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OUT_RELOC(target_bo,
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I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
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0);
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OUT_BATCH(0xdeadbeef);
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ADVANCE_BATCH();
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intel_batchbuffer_flush(batch);
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igt_assert(target_bo->offset != 0);
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} else
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igt_assert(target_bo->offset == 0);
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/* gem_storedw_batches_loop.c is a bit overenthusiastic with
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* creating new batchbuffers - with buffer reuse disabled, the
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* support code will do that for us. */
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@ -118,66 +141,54 @@ store_pipe_control_loop(void)
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drm_intel_bo_map(target_bo, 1);
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buf = target_bo->virtual;
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if (buf[0] != val) {
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fprintf(stderr,
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"value mismatch: cur 0x%08x, stored 0x%08x\n",
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buf[0], val);
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igt_fail(-1);
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}
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buf[0] = 0; /* let batch write it again */
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drm_intel_bo_unmap(target_bo);
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igt_assert(buf[0] == val);
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drm_intel_bo_unmap(target_bo);
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/* Make doublesure that this buffer won't get reused. */
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drm_intel_bo_disable_reuse(target_bo);
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drm_intel_bo_unreference(target_bo);
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val++;
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}
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printf("completed %d writes successfully\n", i);
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}
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int fd;
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int main(int argc, char **argv)
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{
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int fd;
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if (argc != 1) {
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fprintf(stderr, "usage: %s\n", argv[0]);
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igt_fail(-1);
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}
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igt_subtest_init(argc, argv);
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igt_fixture {
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fd = drm_open_any();
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devid = intel_get_drm_devid(fd);
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bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
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if (!bufmgr) {
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fprintf(stderr, "failed to init libdrm\n");
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igt_fail(-1);
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}
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igt_assert(bufmgr);
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igt_skip_on(IS_GEN2(devid) || IS_GEN3(devid));
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igt_skip_on(devid == PCI_CHIP_I965_G); /* has totally broken pipe control */
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if (IS_GEN2(devid) || IS_GEN3(devid)) {
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fprintf(stderr, "no pipe_control on gen2/3\n");
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return 77;
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}
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if (devid == PCI_CHIP_I965_G) {
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fprintf(stderr, "pipe_control totally broken on i965\n");
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return 77;
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}
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/* IMPORTANT: No call to
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* drm_intel_bufmgr_gem_enable_reuse(bufmgr);
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* here because we wan't to have fresh buffers (to trash the tlb)
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* every time! */
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batch = intel_batchbuffer_alloc(bufmgr, devid);
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if (!batch) {
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fprintf(stderr, "failed to create batch buffer\n");
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igt_fail(-1);
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igt_assert(batch);
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}
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store_pipe_control_loop();
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igt_subtest("fresh-buffer")
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store_pipe_control_loop(false);
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igt_subtest("reused-buffer")
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store_pipe_control_loop(true);
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igt_fixture {
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intel_batchbuffer_free(batch);
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drm_intel_bufmgr_destroy(bufmgr);
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close(fd);
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}
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return 0;
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igt_exit();
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}
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