mirror of
https://github.com/tiagovignatti/intel-gpu-tools.git
synced 2026-08-21 21:32:56 +00:00
tools: Added intel_dpio_read and intel_dpio_write
In Valleyview the DPLL and lane control registers are accessible only through side band fabric called DPIO. Added two tools to read and write registers residing in this space. v2: Moved the core read/write functions to lib/intel_dpio.c based on Ben's feedback Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
committed by
Daniel Vetter
parent
082826de6c
commit
4fc76adf31
@@ -3741,5 +3741,18 @@ typedef enum {
|
||||
#define SFUSE_STRAP_DDIC_DETECTED (1<<1)
|
||||
#define SFUSE_STRAP_DDID_DETECTED (1<<0)
|
||||
|
||||
/* Valleyview related items */
|
||||
|
||||
/* Valleyview DPIO registers */
|
||||
#define VLV_DISPLAY_BASE 0x180000
|
||||
#define DPIO_PKT 0x2100
|
||||
#define DPIO_RID (0 << 24)
|
||||
#define DPIO_OP_WRITE (1 << 16)
|
||||
#define DPIO_OP_READ (0 << 16)
|
||||
#define DPIO_PORTID (0x12 << 8)
|
||||
#define DPIO_BYTE (0xf << 4)
|
||||
#define DPIO_BUSY (1 << 0)
|
||||
#define DPIO_DATA 0x2104
|
||||
#define DPIO_REG 0x2108
|
||||
|
||||
#endif /* _I810_REG_H */
|
||||
|
||||
Reference in New Issue
Block a user