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Add support for flag register f1 on Ivy bridge

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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
This commit is contained in:
Xiang, Haihao 2012-07-17 15:05:31 +08:00 committed by Damien Lespiau
parent 2f772dd67b
commit 3ffbe96c1e
4 changed files with 26 additions and 9 deletions
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12
assembler/src/brw_structs.h
View File

@ -1135,7 +1135,8 @@ struct brw_instruction
GLuint src0_width:3; /* 0x001c0000 */ GLuint src0_width:3; /* 0x001c0000 */
GLuint src0_vert_stride:4; /* 0x01e00000 */ GLuint src0_vert_stride:4; /* 0x01e00000 */
GLuint flag_subreg_nr:1; /* 0x02000000 */ GLuint flag_subreg_nr:1; /* 0x02000000 */
GLuint pad:6; /* 0xfc000000 */ GLuint flag_reg_nr:1; /* 0x04000000 */
GLuint pad:5; /* 0xf8000000 */
} da1; } da1;
struct struct
@ -1149,7 +1150,8 @@ struct brw_instruction
GLuint src0_width:3; GLuint src0_width:3;
GLuint src0_vert_stride:4; GLuint src0_vert_stride:4;
GLuint flag_subreg_nr:1; GLuint flag_subreg_nr:1;
GLuint pad:6; GLuint flag_reg_nr:1;
GLuint pad:5;
} ia1; } ia1;
struct struct
@ -1166,7 +1168,8 @@ struct brw_instruction
GLuint pad0:1; GLuint pad0:1;
GLuint src0_vert_stride:4; GLuint src0_vert_stride:4;
GLuint flag_subreg_nr:1; GLuint flag_subreg_nr:1;
GLuint pad1:6; GLuint flag_reg_nr:1;
GLuint pad1:5;
} da16; } da16;
struct struct
@ -1183,7 +1186,8 @@ struct brw_instruction
GLuint pad0:1; GLuint pad0:1;
GLuint src0_vert_stride:4; GLuint src0_vert_stride:4;
GLuint flag_subreg_nr:1; GLuint flag_subreg_nr:1;
GLuint pad1:6; GLuint flag_reg_nr:1;
GLuint pad1:5;
} ia16; } ia16;
struct struct

2
assembler/src/disasm.c
View File

@ -779,7 +779,7 @@ int disasm (FILE *file, struct brw_instruction *inst)
if (inst->header.predicate_control) { if (inst->header.predicate_control) {
string (file, "("); string (file, "(");
err |= control (file, "predicate inverse", pred_inv, inst->header.predicate_inverse, NULL); err |= control (file, "predicate inverse", pred_inv, inst->header.predicate_inverse, NULL);
string (file, "f0"); format (file, "f%d", inst->bits2.da1.flag_reg_nr);
if (inst->bits2.da1.flag_subreg_nr) if (inst->bits2.da1.flag_subreg_nr)
format (file, ".%d", inst->bits2.da1.flag_subreg_nr); format (file, ".%d", inst->bits2.da1.flag_subreg_nr);
if (inst->header.access_mode == BRW_ALIGN_1) if (inst->header.access_mode == BRW_ALIGN_1)

1
assembler/src/gen4asm.h
View File

@ -49,6 +49,7 @@ struct direct_reg {
struct condition { struct condition {
int cond; int cond;
int flag_reg_nr;
int flag_subreg_nr; int flag_subreg_nr;
}; };

20
assembler/src/gram.y
View File

@ -389,8 +389,10 @@ unaryinstruction:
if (set_instruction_src0(&$$, &$7) != 0) if (set_instruction_src0(&$$, &$7) != 0)
YYERROR; YYERROR;
if ($3.flag_subreg_nr != -1) if ($3.flag_subreg_nr != -1) {
$$.bits2.da1.flag_reg_nr = $3.flag_reg_nr;
$$.bits2.da1.flag_subreg_nr = $3.flag_subreg_nr; $$.bits2.da1.flag_subreg_nr = $3.flag_subreg_nr;
}
if (gen_level < 6 && if (gen_level < 6 &&
get_type_size($$.bits1.da1.dest_reg_type) * (1 << $$.header.execution_size) == 64) get_type_size($$.bits1.da1.dest_reg_type) * (1 << $$.header.execution_size) == 64)
@ -419,8 +421,10 @@ binaryinstruction:
if (set_instruction_src1(&$$, &$8) != 0) if (set_instruction_src1(&$$, &$8) != 0)
YYERROR; YYERROR;
if ($3.flag_subreg_nr != -1) if ($3.flag_subreg_nr != -1) {
$$.bits2.da1.flag_reg_nr = $3.flag_reg_nr;
$$.bits2.da1.flag_subreg_nr = $3.flag_subreg_nr; $$.bits2.da1.flag_subreg_nr = $3.flag_subreg_nr;
}
if (gen_level < 6 && if (gen_level < 6 &&
get_type_size($$.bits1.da1.dest_reg_type) * (1 << $$.header.execution_size) == 64) get_type_size($$.bits1.da1.dest_reg_type) * (1 << $$.header.execution_size) == 64)
@ -449,8 +453,10 @@ binaryaccinstruction:
if (set_instruction_src1(&$$, &$8) != 0) if (set_instruction_src1(&$$, &$8) != 0)
YYERROR; YYERROR;
if ($3.flag_subreg_nr != -1) if ($3.flag_subreg_nr != -1) {
$$.bits2.da1.flag_reg_nr = $3.flag_reg_nr;
$$.bits2.da1.flag_subreg_nr = $3.flag_subreg_nr; $$.bits2.da1.flag_subreg_nr = $3.flag_subreg_nr;
}
if (gen_level < 6 && if (gen_level < 6 &&
get_type_size($$.bits1.da1.dest_reg_type) * (1 << $$.header.execution_size) == 64) get_type_size($$.bits1.da1.dest_reg_type) * (1 << $$.header.execution_size) == 64)
@ -1849,7 +1855,8 @@ accreg: ACCREG subregnum
flagreg: FLAGREG subregnum flagreg: FLAGREG subregnum
{ {
if ($1 > 0) { if ((gen_level <= 6 && $1) > 0 ||
(gen_level > 6 && $1 > 1)) {
fprintf(stderr, fprintf(stderr,
"flag register number %d out of range\n", $1); "flag register number %d out of range\n", $1);
YYERROR; YYERROR;
@ -2291,6 +2298,7 @@ imm32: exp { $$.r = imm32_d; $$.u.d = $1; }
predicate: /* empty */ predicate: /* empty */
{ {
$$.header.predicate_control = BRW_PREDICATE_NONE; $$.header.predicate_control = BRW_PREDICATE_NONE;
$$.bits2.da1.flag_reg_nr = 0;
$$.bits2.da1.flag_subreg_nr = 0; $$.bits2.da1.flag_subreg_nr = 0;
$$.header.predicate_inverse = 0; $$.header.predicate_inverse = 0;
} }
@ -2301,6 +2309,7 @@ predicate: /* empty */
* set a predicate for one flag register and conditional * set a predicate for one flag register and conditional
* modification on the other flag register. * modification on the other flag register.
*/ */
$$.bits2.da1.flag_reg_nr = ($3.reg_nr & 0xF);
$$.bits2.da1.flag_subreg_nr = $3.subreg_nr; $$.bits2.da1.flag_subreg_nr = $3.subreg_nr;
$$.header.predicate_inverse = $2; $$.header.predicate_inverse = $2;
} }
@ -2360,11 +2369,13 @@ saturate: /* empty */ { $$ = BRW_INSTRUCTION_NORMAL; }
conditionalmodifier: condition conditionalmodifier: condition
{ {
$$.cond = $1; $$.cond = $1;
$$.flag_reg_nr = 0;
$$.flag_subreg_nr = -1; $$.flag_subreg_nr = -1;
} }
| condition DOT flagreg | condition DOT flagreg
{ {
$$.cond = $1; $$.cond = $1;
$$.flag_reg_nr = ($3.reg_nr & 0xF);
$$.flag_subreg_nr = $3.subreg_nr; $$.flag_subreg_nr = $3.subreg_nr;
} }
@ -2848,6 +2859,7 @@ void set_instruction_predicate(struct brw_instruction *instr,
{ {
instr->header.predicate_control = predicate->header.predicate_control; instr->header.predicate_control = predicate->header.predicate_control;
instr->header.predicate_inverse = predicate->header.predicate_inverse; instr->header.predicate_inverse = predicate->header.predicate_inverse;
instr->bits2.da1.flag_reg_nr = predicate->bits2.da1.flag_reg_nr;
instr->bits2.da1.flag_subreg_nr = predicate->bits2.da1.flag_subreg_nr; instr->bits2.da1.flag_subreg_nr = predicate->bits2.da1.flag_subreg_nr;
} }